LFXP2-30E-5FN484C LATTICE SEMICONDUCTOR, LFXP2-30E-5FN484C Datasheet - Page 20
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LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-484
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet
1.LFXP2-5E-5TN144C.pdf
(93 pages)
Specifications of LFXP2-30E-5FN484C
No. Of Logic Blocks
29000
No. Of Macrocells
14500
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
363
Clock Management
PLL
Total Ram Bits
387Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode
3. Read-Before-Write – When new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-17.
Figure 2-17. Memory Core Reset
For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18.
The GSR input to the EBR is always asynchronous.
Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram
address) does not appear on the output. This mode is supported for all data widths.
is supported for all data widths.
This mode is supported for x9, x18 and x36 data widths.
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-17
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeXP2 Family Data Sheet
Port A[17:0]
Port B[17:0]
Architecture