LFXP2-30E-5FN484C LATTICE SEMICONDUCTOR, LFXP2-30E-5FN484C Datasheet - Page 92
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LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-484
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet
1.LFXP2-5E-5TN144C.pdf
(93 pages)
Specifications of LFXP2-30E-5FN484C
No. Of Logic Blocks
29000
No. Of Macrocells
14500
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
363
Clock Management
PLL
Total Ram Bits
387Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
www.latticesemi.com
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
April 2008
Revision History
September 2007
February 2008
April 2008
May 2007
Date
Version
01.1
01.2
01.3
01.4
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Architecture
Section
—
Initial release.
Added JTAG Port Timing Waveforms diagram.
Updated sysCLOCK PLL Timing table.
Added Thermal Management text section.
Added LVCMOS33D to Supported Output Standards table.
Clarified: “This Flash can be programmed through either the JTAG or
Slave SPI ports of the device. The SRAM configuration space can also
be infinitely reconfigured through the JTAG and Master SPI ports.”
Added External Slave SPI Port to Serial TAG Memory section. Updated
Serial TAG Memory diagram.
Updated Flash Programming Specifications table.
Added “8W” specification to Hot Socketing Specifications table.
Updated Timing Tables
Clarifications for IIH in DC Electrical Characteristics table.
Added LVCMOS33D section
Updated DOA and DOA (Regs) to EBR Timing diagrams.
Removed Master Clock Frequency and Duty Cycle sections from the
LatticeXP2 sysCONFIG Port Timing Specifications table. These are
listed on the On-chip Oscillator and Configuration Master Clock Charac-
teristics table.
Changed CSSPIN to CSSPISN in description of t
parameters. Removed t
Clarified On-chip Oscillator documentation
Added Switching Test Conditions
Added “True LVDS Pairs Bonding Out per Bank,” “DDR Banks Bonding
Out per I/O Bank,” and “PCI capable I/Os Bonding Out per Bank” to Pin
Information Summary in place of previous blank table “PCI and DDR
Capabilities of the Device-Package Combinations”
Removed pinout listing. This information is available on the LatticeXP2
product web pages
Added XP2-17 “8W” and all other family OPNs.
Updated Absolute Maximum Ratings footnotes.
Updated Recommended Operating Conditions Table footnotes.
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Updated Programming and Erase Flash Supply Current Table
Updated Register to Register Performance Table
Updated LatticeXP2 External Switching Characteristics Table
Updated LatticeXP2 Internal Switching Characteristics Table
Updated sysCLOCK PLL Timing Table
LatticeXP2 Family Data Sheet
7-1
SOE
Change Summary
parameter.
Revision History
Preliminary Data Sheet DS1009
SCS
, t
SCSS
, and t
SCSH