LFXP2-30E-5FN484C LATTICE SEMICONDUCTOR, LFXP2-30E-5FN484C Datasheet - Page 25
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LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
IC, LATTICEXP2 FPGA, 435MHZ, FPBGA-484
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeXP2r
Datasheet
1.LFXP2-5E-5TN144C.pdf
(93 pages)
Specifications of LFXP2-30E-5FN484C
No. Of Logic Blocks
29000
No. Of Macrocells
14500
Family Type
LatticeXP2
No. Of Speed Grades
5
No. Of I/o's
363
Clock Management
PLL
Total Ram Bits
387Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
MULTADDSUB sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. The user can enable the input, output and pipeline registers. Figure 2-22
shows the MULTADDSUB sysDSP element.
Figure 2-22. MULTADDSUB
Multiplicand A0
Multiplicand A1
Multiplier B0
Multiplier B1
Signed A
Signed B
Addn
Shift Register B Out
Shift Register B In
n
n
Input Data
Register B
Input Data
Register B
n
n
n
n
n
Register
Register
Register
Input
Input
Input
m
m
Input Data
Register A
Input Data
Register A
m
Shift Register A Out
m
m
Shift Register A In
m
m
Pipeline
Register
Register
Register
Pipeline
Pipeline
Pipe
Pipe
Pipe
Reg
Reg
Reg
m
n
m
n
2-22
To Add/Sub
To Add/Sub
To Add/Sub
Multiplier
Multiplier
Register
Pipeline
Register
Pipeline
x
x
(default)
(default)
m+n
m+n
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST (RST0,RST1,RST2,RST3)
Add/Sub
LatticeXP2 Family Data Sheet
(default)
m+n+1
(default)
m+n+1
Architecture
Output