5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 40

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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MAX V Device Handbook
Slew-Rate Control
Open-Drain Output
Programmable Ground Pins
Bus-Hold
1
The output buffer for each MAX V device I/O pin has a programmable output
slew-rate control that can be configured for low noise or high-speed performance. A
faster slew rate provides high-speed transitions for high-performance systems.
However, these fast transitions may introduce noise transients into the system. A slow
slew rate reduces system noise, but adds a nominal output delay to rising and falling
edges. The lower the voltage standard (for example, 1.8-V LVTTL) the larger the
output delay when slow slew is enabled. Each I/O pin has an individual slew-rate
control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate
control affects both the rising and falling edges. If no slew-rate control is specified, the
Quartus II software defaults to a fast slew rate.
The slew-rate control feature can be used simultaneously with the programmable
drive strength feature.
MAX V devices provide an optional open-drain (equivalent to open-collector) output
for each I/O pin. This open-drain output enables the device to provide system-level
control signals (for example, interrupt and write enable signals) that can be asserted
by any of several devices. This output can also provide an additional wired-OR plane.
Each unused I/O pin on MAX V devices can be used as an additional ground pin.
This programmable ground feature does not require the use of the associated LEs in
the device. In the Quartus II software, unused pins can be set as programmable GND
on a global default basis or they can be individually assigned. Unused pins also have
the option of being set as tri-stated input pins.
Each MAX V device I/O pin provides an optional bus-hold feature. The bus-hold
circuitry can hold the signal on an I/O pin at its last-driven state. Because the bus-
hold feature holds the last-driven state of the pin until the next input signal is present,
an external pull-up or pull-down resistor is not necessary to hold a signal level when
the bus is tri-stated.
The bus-hold circuitry also pulls un-driven pins away from the input threshold
voltage where noise can cause unintended high-frequency switching. You can select
this feature individually for each I/O pin. The bus-hold output will drive no higher
than V
device cannot use the programmable pull-up option.
The bus-hold circuitry is only active after the device has fully initialized. The bus-hold
circuit captures the value on the pin present at the moment user mode is entered.
CCIO
to prevent overdriving signals. If the bus-hold feature is enabled, the
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
I/O Structure