XC2C384-10TQG144C Xilinx Inc, XC2C384-10TQG144C Datasheet

IC, CPLD, 384 MACROCELL, 7.1NS, TQFP-144

XC2C384-10TQG144C

Manufacturer Part Number

XC2C384-10TQG144C

Description

IC, CPLD, 384 MACROCELL, 7.1NS, TQFP-144

Manufacturer

Xilinx Inc

Series

CoolRunner IIr

Datasheets

1.XC2C32A-6QFG32C.pdf (16 pages)

2.XC2C384-10TQG144C.pdf (26 pages)

Specifications of XC2C384-10TQG144C

No. Of Macrocells

384

No. Of I/o's

118

Propagation Delay

7.1ns

Global Clock Setup Time

3.3ns

Frequency

125MHz

Supply Voltage Range

1.7V To 1.9V

Programmable Type

In System Programmable

Delay Time Tpd(1) Max

9.2ns

Voltage Supply - Internal

1.7 V ~ 1.9 V

Number Of Logic Elements/blocks

Number Of Macrocells

384

Number Of Gates

9000

Number Of I /o

118

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

144-TQFP, 144-VQFP

Features

JTAG

Voltage

1.8V

Memory Type

CMOS

Rohs Compliant

Yes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Logic Elements/cells

Lead Free Status / RoHS Status

Lead free / RoHS Compliant, Lead free / RoHS Compliant

Other names

122-1406

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DS095 (v3.2) March 8, 2007

Features

•

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

DS095 (v3.2) March 8, 2007

Product Specification

Optimized for 1.8V systems

Industry’s best 0.18 micron CMOS CPLD

Available in multiple package options

Advanced system features

As fast as 7.1 ns pin-to-pin delays

As low as 14 μA quiescent current

Optimized architecture for effective logic synthesis

Multi-voltage I/O operation — 1.5V to 3.3V

144-pin TQFP with 118 user I/O

208-pin PQFP with 173 user I/O

256-ball FT (1.0mm) BGA with 212 user I/O

324-ball FG (1.0mm) BGA with 240 user I/O

Pb-free available for all packages

Fastest in system programming

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

Unsurpassed low power management

Four separate I/O banks

RealDigital 100% CMOS product term generation

Flexible clocking modes

Global signal options with macrocell control

Advanced design security

PLA architecture

Open-drain output option for Wired-OR and LED

drive

Optional bus-hold, 3-state or weak pullup on

selected I/O pins

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

Hot pluggable

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

1.8V ISP using IEEE 1532 (JTAG) interface

DataGATE enable (DGE) signal control

Optional DualEDGE triggered registers

Clock divider (divide by 2,4,6,8,10,12,14,16)

CoolCLOCK

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Superior pinout retention

100% product term routability across function

block

SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

www.xilinx.com

XC2C384 CoolRunner-II CPLD

Product Specification

Description

The CoolRunner-II 384-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

This device consists of twenty four Function Blocks

inter-connected by a low power Advanced Interconnect

Matrix (AIM). The AIM feeds 40 true and complement inputs

to each Function Block. The Function Blocks consist of a 40

by 56 P-term PLA and 16 macrocells which contain numer-

ous configuration bits that allow for combinational or regis-

tered modes of operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as direct input registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

Related parts for XC2C384-10TQG144C

XC2C384-10TQG144C Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS095 (v3.2) March 8, 2007 Product Specification 0 XC2C384 CoolRunner-II CPLD Product Specification 0 0 Description The CoolRunner-II 384-macrocell device is designed for both high performance and low power applications ...

Page 2

... LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. 1). This device is also Table 1: I/O Standards for XC2C384 IOSTANDARD Attribute LVTTL LVCMOS33 ...

Page 3

... CC CCIO V = 1.9V 3.6V CC CCIO MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO www.xilinx.com XC2C384 CoolRunner-II CPLD Value Units –0.5 to 2.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –65 to +150 °C +150 °C Min Max Units 1.7 1 ...

Page 4

... XC2C384 CoolRunner-II CPLD LVCMOS and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter V Input source voltage ...

Page 5

... –8 mA CCIO mA CCIO , also peak to peak AC noise on V CCIO REF of receiving devices. REF Test Conditions V www.xilinx.com XC2C384 CoolRunner-II CPLD Min. Max. - 0.4 - 0.2 Min. Max. 1.4 3 CCIO CCIO 0 0 CCIO CCIO Min. Typ Max. 2.3 2.5 2.7 1.15 1 ...

Page 6

... XC2C384 CoolRunner-II CPLD Symbol Parameter V Low level input voltage IL V High level output voltage OH V Low level output voltage OL 6 Test Conditions Min. –0 – CCIO CCIO mA 1.4V OL CCIO www.xilinx.com Typ Max – 0.1 REF – 0 0.4 DS095 (v3.2) March 8, 2007 ...

Page 7

... OR array (one counter per function block) SYSTEM2 the maximum external frequency using one p-term while F EXT1 SU1 CO 4. Typical configuration current during DS095 (v3.2) March 8, 2007 Product Specification Parameter mA. CONFIG www.xilinx.com XC2C384 CoolRunner-II CPLD -7 -10 Min. Max. Min. Max. - 7.1 - 9.2 - 7.5 - 10.0 4 ...

Page 8

... XC2C384 CoolRunner-II CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Direct data register input delay DIN T Global Clock buffer delay GCK T Global set/reset buffer delay GSR T Global 3-state buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable delay ...

Page 9

... GCK GSR - OUT , DIN GCK GSR - OUT , DIN GCK GSR - OUT Switching Test Conditions DS095_02_053103 PD www.xilinx.com XC2C384 CoolRunner-II CPLD -7 -10 Max. Min. Max. 0.5 - 2.0 1.2 - 3.0 1.2 - 3.0 3.0 - 4.0 0.8 2.5 - -0.5 - 0.0 0.8 2.5 - -0.50 - 0.00 1.0 2 ...

Page 10

... VO (Output Volts) Figure 4: Typical I/V Curves for XC2C384 Pin Descriptions (Continued) Function I/O Block FT256 FG324 Bank 2(GTS2 2(GTS3 2(GTS0 2(GTS1) ...

Page 11

... DS095 (v3.2) March 8, 2007 Product Specification Pin Descriptions (Continued) I/O Function FT256 FG324 Bank Block www.xilinx.com XC2C384 CoolRunner-II CPLD Macro- cell TQ144 PQ208 FT256 FG324 133 - 132 - 189 188 187 131 186 185 A8 D10 15 130 184 E11 C10 16 129 183 E10 B10 ...

Page 12

... XC2C384 CoolRunner-II CPLD Pin Descriptions (Continued) Function Macro- Block cell TQ144 PQ208 7(CDRST 7(GCK1 7(GCK0 8(GCK2 8(DGE Pin Descriptions (Continued) I/O Function FT256 FG324 Bank Block P2 AB2 AA2 AA1 AB3 AA4 AA5 AB4 AB5 AA6 1 10 www.xilinx.com Macro- cell TQ144 PQ208 ...

Page 13

... AA9 AB9 W10 Y10 AA10 AB10 AB11 W11 AA11 Y11 1 14 www.xilinx.com XC2C384 CoolRunner-II CPLD Macro- cell TQ144 PQ208 FT256 FG324 B16 C21 G11 C20 3 112 160 C14 B22 4 113 161 B15 B21 A16 A22 114 162 B13 A21 13 115 163 ...

Page 14

... XC2C384 CoolRunner-II CPLD Pin Descriptions (Continued) Function Macro- Block cell TQ144 PQ208 116 165 166 117 167 168 15 13 118 169 119 170 15 16 120 171 16 1 103 149 148 16 3 102 147 146 145 101 144 100 143 14 Pin Descriptions (Continued) ...

Page 15

... T14 Y18 3 22 N11 AA19 3 22 P11 Y17 3 22 M11 AA18 3 22 T13 AB18 3 22 www.xilinx.com XC2C384 CoolRunner-II CPLD Macro- cell TQ144 PQ208 FT256 FG324 1 80 114 P16 V22 2 - 115 N16 U20 3 81 116 L14 U21 4 - 117 M14 U22 5 - 118 ...

Page 16

... XC2C384 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type TQ144 TCK TDI TDO TMS V (JTAG supply CCAUX voltage) Power internal ( 37 Power Bank 1 I 27, 55 CCIO1 Power Bank 2 I CCIO2 Power Bank 3 I 73, 93 CCIO3 Power Bank 4 I/O (V ...

Page 17

... R XC2C384 JTAG, Power/Ground, No Connect Pins and Total User I/O (Continued) Pin Type TQ144 Ground 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 No connects Total user I/O (includes dual function pins) DS095 (v3.2) March 8, 2007 Product Specification PQ208 13, 24, 42, 52, F11, F6, G10, G7, G8, ...

Page 18

... Part Number Spacing XC2C384-7TQ144C 0.5mm XC2C384-10TQ144C 0.5mm XC2C384-7PQ208C 0.5mm XC2C384-10PQ208C 0.5mm XC2C384-7FT256C 1.0mm XC2C384-10FT256C 1.0mm XC2C384-7FG324C 1.0mm XC2C384-10FG324C 1.0mm XC2C384-7TQG144C 0.5mm XC2C384-10TQG144C 0.5mm XC2C384-7PQG208C 0.5mm XC2C384-10PQG208C 0.5mm XC2C384-7FTG256C 1.0mm XC2C384-10FTG256C 1.0mm XC2C384-7FGG324C 1.0mm XC2C384-10FGG324C 1.0mm XC2C384-10TQ144I 0.5mm XC2C384-10PQ208I 0.5mm XC2C384-10FT256I 1.0mm XC2C384-10FG324I 1 ...

Page 19

... R Device Part Marking Device Type Package Speed Operating Range DS095 (v3.2) March 8, 2007 Product Specification R XC2Cxxx TQ144 7C Part marking for non-chip scale package Figure 5: Sample Package with Part Marking www.xilinx.com XC2C384 CoolRunner-II CPLD This line not related to device part number 19 ...

Page 20

... XC2C384 CoolRunner-II CPLD (1) I/O 2 (1) I/O 3 I/O 4 (1) I/O 5 (1) I AUX 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I CCIO1 I/O 28 GND 29 (2) I/O 30 I/O 31 (2) I/O 32 I/O 33 I/O ...

Page 21

... I I/O I/O( GND DS095 (v3.2) March 8, 2007 Product Specification PQ208 Top View Figure 7: PQ208 Plastic Quad Flat Package www.xilinx.com XC2C384 CoolRunner-II CPLD GND 156 I/O 155 I/O 154 I/O 153 I/O 152 I/O 151 I/O 150 I/O 149 I/O ...

Page 22

... XC2C384 CoolRunner-II CPLD A I/O I/O I/O I/O B I/O I/O I/O I/O C I/O I/O I/O I/O D I/O I/O I/O I/O VCC E I/O I/O I/O I/O F I/O I/O I/O I/O G I/O I/O I/O I/O H I/O I/O I/O I/O J I/O I/O I/O I/O K I/O ...

Page 23

... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O FG324 Bottom View Figure 9: FG324 Fine Pitch BGA www.xilinx.com XC2C384 CoolRunner-II CPLD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

Page 24

... Corrected typo on page 1. 324-ball FG BGA package has ball pitch of 1.0mm 1/26/04 2.2 Added links to Application notes and Data sheets 5/7/04 2.3 Corrected error in package dimensions of XC2C384-10TQ144I 8/03/04 2.4 Pb-free documentation 10/01/04 2.5 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics 01/30/05 2 ...

Page 25

... OL for -6 speed grade, and to t OEM , t ,and t for the -7 speed grade. Values now match the software. There were PHD SUEC for LVCMOS18; removed note for V IL www.xilinx.com XC2C384 CoolRunner-II CPLD Revision , SUD SU1 SU2 and F . Changes to -10 speed grade: T EXT2 , F , and F ...

Page 26

... XC2C384 CoolRunner-II CPLD 26 www.xilinx.com R DS095 (v3.2) March 8, 2007 Product Specification ...

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