CAT24WC128WI CATALYST SEMICONDUCTOR, CAT24WC128WI Datasheet - Page 3

• Manufacturer Part Number: CAT24WC128WI
• Description: EEPROM SERIAL 128K, 24WC128, SOIC8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT24WC128WI

• Memory Size: 128Kbit
• Clock Frequency: 1MHz
• Supply Voltage Range: 1.8V To 6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Memory Configuration: 16384 X 8
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes

V
Output Load is 1 TTL Gate and 100pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
The CAT24WC128 supports the I
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
CC
F
t
t
t
t
t
t
t
t
t
t
t
t
t
AA
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
DH
WR
t
SCL
t
(1)
(1)
PUW
PUR
PUR
= +1.8V to +6V, unless otherwise specified
(1)
and t
PUW
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
are the delays required from the time V
Power-Up to Read Operation
Power-Up to Write Operation
2
C Bus data transmis-
CC
is stable until the specified operation can be initiated.
0.1
4.0
4.0
4.7
100
4.7
4.7
4.0
0
100
3
100
3.5
1.0
300
10
STOP conditions for bus access. The CAT24WC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
0.05
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
400
0.9
0.3
300
10
1
1
0.05
0.5
0.25
0.6
0.4
0.25
0
100
0.25
50
1000
0.55
0.3
100
10
Doc. No. 1038, Rev. D
ms
ms
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ms