CAT24WC128WI CATALYST SEMICONDUCTOR, CAT24WC128WI Datasheet - Page 4

• Manufacturer Part Number: CAT24WC128WI
• Description: EEPROM SERIAL 128K, 24WC128, SOIC8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT24WC128WI

• Memory Size: 128Kbit
• Clock Frequency: 1MHz
• Supply Voltage Range: 1.8V To 6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Memory Configuration: 16384 X 8
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes

This input, when tied to GND, allows write operations to
the entire memory.
entire memory is write protected. When left floating,
memory is unprotected.
The serial clock input clocks all data transferred into or
out of the device.
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
Doc. No. 1038, Rev. D
SDA OUT
Write Protect
SDA IN
Serial Clock
Serial Data/Address
SCL
SCL
SDA
t SU:STA
When this pin is tied to Vcc, the
SDA
SCL
t F
8TH BIT
BYTE n
t HD:STA
START BIT
t LOW
t AA
ACK
t HD:DAT
t HIGH
t LOW
STOP
CONDITION
4
The features of the I
follows:
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
(1) Data transfer may be initiated only when the bus
(2) During a data transfer, the data line must remain
t DH
is not busy.
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
t SU:DAT
t WR
t R
STOP BIT
START
CONDITION
2
C bus protocol are defined as
t SU:STO
t BUF
ADDRESS