CAT24WC128WI CATALYST SEMICONDUCTOR, CAT24WC128WI Datasheet - Page 7

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CAT24WC128WI

Manufacturer Part Number
CAT24WC128WI
Description
EEPROM SERIAL 128K, 24WC128, SOIC8
Manufacturer
CATALYST SEMICONDUCTOR
Datasheet

Specifications of CAT24WC128WI

Memory Size
128Kbit
Clock Frequency
1MHz
Supply Voltage Range
1.8V To 6V
Memory Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (18-Jun-2010)
Package /
RoHS Compliant
Memory Configuration
16384 X 8
Interface Type
I2C, Serial, 2-Wire
Rohs Compliant
Yes
*
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24WC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC128 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
=Don't Care Bit
BUS ACTIVITY:
SDA LINE
MASTER
SDA
SCL
S
S
A
R
T
T
ADDRESS
SLAVE
BUS ACTIVITY:
SDA LINE
MASTER
C
A
K
*
DATA OUT
8TH BIT
*
8
S
R
A 15 –A 8
S
T
A
T
ADDRESS
BYTE ADDRESS
SLAVE
A
C
K
7
A
C
K
A 7 –A 0
data. The CAT24WC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to re-
spond with an acknowledge, thus sending the STOP
condition.
The data being transmitted from CAT24WC128 is out-
putted sequentially with data from address N followed
by data from address N+1. The READ operation ad-
dress counter increments all of the CAT24WC128 ad-
dress bits so that the entire memory array can be read
during one operation. If more than E (where E=16383)
bytes are read out, the counter will ‘wrap around’ and
continue to clock out data bytes.
9
NO ACK
DATA
C
A
K
S
S
A
R
T
T
N
O
A
C
K
ADDRESS
P
S
O
P
T
SLAVE
STOP
C
A
K
24WC128 F10
DATA
Doc. No. 1038, Rev. D
N
O
A
C
K
O
S
P
P
T

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