IDT72V261LA10PFG INTEGRATED DEVICE TECHNOLOGY, IDT72V261LA10PFG Datasheet
IDT72V261LA10PFG
Specifications of IDT72V261LA10PFG
Related parts for IDT72V261LA10PFG
IDT72V261LA10PFG Summary of contents
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... LOGIC PRS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • The limitation of the frequency of one clock input with ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V261LA/72V271LA support two different timing modes of operation: IDT Standard mode or First ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V261LA/72V271LA has internal registers for these offsets. De- fault settings are stated in the ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 IDT72V261LA ⎯ 16,384 x 9 − BIT 8 7 EMPTY OFFSET (LSB) REG. DEFAULT VALUE 07FH LOW at Master Reset 3FFH ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 When EF goes HIGH, Retransmit setup is complete and read opera- tions may begin starting with the first location in memory. Since IDT Standard mode is selected, ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 WRITE CLOCK (WCLK) A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronous and ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS RSR t t ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES JANUARY 30, 2009 ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES JANUARY 30, 2009 ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 RCLK t ENH t ENS t RTS REN WCLK WEN t ENS RT EF PAE HF PAF NOTES: ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 RCLK t ENH t ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 CLK t t CLKH CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel Loading ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 CLKH CLKL WCLK t t ENS ENH WEN PAF D - (m+1) words in FIFO RCLK REN NOTES PAF offset ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any ...
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IDT72V261LA/72V271LA 3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V261LA can easily be adapted to applications requiring depths greater than 16,384 and 32,768 for the IDT72V271LA with a 9-bit ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts available. For specific ...
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... CC1 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...