IDT72V261LA10PFG INTEGRATED DEVICE TECHNOLOGY, IDT72V261LA10PFG Datasheet - Page 14

• Manufacturer Part Number: IDT72V261LA10PFG
• Description: IC, FIFO, 144K, 16KX9, 3.3V, TQFP64
• Manufacturer: INTEGRATED DEVICE TECHNOLOGY

Specifications of IDT72V261LA10PFG

• Memory Size: 144Kbit
• Data Bus Width: 9bit
• Clock Frequency: 50MHz
• Access Time: 12ns
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 64
• Operating Temperature Range: 0°C To
• Memory Configuration: 16384 X 9
• Fifo Function: Synchronous
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FWFT mode, the total number of writes necessary to deassert IR is one
greater than needed to assert FF in IDT Standard mode.
IR are double register-buffered outputs.
EMPTY FLAG (EF/OR)
Flag (EF) function is selected. When the FIFO is empty, EF will go
LOW, inhibiting further read operations. When EF is HIGH, the FIFO is
not empty. See Figure 8, Read Cycle, Empty Flag and First Word
Latency Timing (IDT Standard Mode), for the relevant timing informa-
tion.
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs. OR stays LOW after the RCLK LOW to
HIGH transition that shifts the last word from the FIFO memory to the
outputs. OR goes HIGH only with a true read (RCLK with REN =
LOW). The previous data stays at the outputs, indicating the last word
was read. Further data reads are inhibited until OR goes LOW again.
See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
FWFT mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
FIFO reaches the almost-full condition. In IDT Standard mode, if no
reads are performed after reset (MRS), PAF will go LOW after (D - m)
words are written to the FIFO. The PAF will go LOW after (16,384-m)
writes for the IDT72V261LA and (32,768-m) writes for the IDT72V271LA.
The offset “m” is the full offset value. The default setting for this value is
stated in the footnote of Table 1.
the IDT72V261LA and (32,769-m) writes for the IDT72V271LA, where
m is the full offset value. The default setting for this value is stated in
the footnote of Table 2.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
FF/IR is synchronous and updated on the rising edge of WCLK. FF/
This is a dual purpose pin. In the IDT Standard mode, the Empty
In FWFT mode, the Output Ready (OR) function is selected. OR
In IDT Standard mode, EF is a double register-buffered output. In
The Programmable Almost-Full flag (PAF) will go LOW when the
In FWFT mode, the PAF will go LOW after (16,385-m) writes for
EF/OR is synchronous and updated on the rising edge of RCLK.
14
dard and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE
will go LOW when there are n words or less in the FIFO. The offset “n”
is the empty offset value. The default setting for this value is stated in
the footnote of Table 1.
less in the FIFO. The default setting for this value is stated in the
footnote of Table 2.
Standard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
the FIFO beyond half-full sets HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or
equal to half of the total depth of the device; the rising RCLK edge that
accomplishes this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where
D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385
for the IDT72V261LA and 32,769 for the IDT72V271LA.
for the relevant timing information. Because HF is updated by both
RCLK and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
See Figure 16, Programmable Almost-Full Flag Timing (IDT Stan-
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the
In FWFT mode, the PAE will go LOW when there are n+1 words or
See Figure 17, Programmable Almost-Empty Flag Timing (IDT
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS),
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
8
) are data outputs for 9-bit wide data.
0
-Q
8
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 30, 2009