IDT72V261LA10PFG INTEGRATED DEVICE TECHNOLOGY, IDT72V261LA10PFG Datasheet - Page 12

• Manufacturer Part Number: IDT72V261LA10PFG
• Description: IC, FIFO, 144K, 16KX9, 3.3V, TQFP64
• Manufacturer: INTEGRATED DEVICE TECHNOLOGY

Specifications of IDT72V261LA10PFG

• Memory Size: 144Kbit
• Data Bus Width: 9bit
• Clock Frequency: 50MHz
• Access Time: 12ns
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 64
• Operating Temperature Range: 0°C To
• Memory Configuration: 16384 X 9
• Fifo Function: Synchronous
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
CONTROLS:
MASTER RESET (MRS)
a LOW state. This operation sets the internal read and write pointers to
the first location of the RAM array. PAE will go LOW, PAF will go
HIGH, and HF will go HIGH.
along with EF and FF are selected. EF will go LOW and FF will go
HIGH. If FWFT is HIGH, then the First Word Fall Through mode
(FWFT), along with IR and OR, are selected. OR will go HIGH and IR
will go LOW.
127 words from the empty boundary and PAF is assigned a threshold
127 words from the full boundary; 127 words corresponds to an offset
value of 07FH. Following Master Reset, parallel loading of the offsets
is permitted, but not serial loading.
old 1,023 words from the empty boundary and PAF is assigned a thresh-
old 1,023 words from the full boundary; 1,023 words corresponds to an
offset value of 3FFH. Following Master Reset, serial loading of the
offsets is permitted, but not parallel loading.
describing the LD pin for further details.)
A Master Reset is required after power up, before a write operation can
take place. MRS is asynchronous.
PARTIAL RESET (PRS)
a LOW state. As in the case of the Master Reset, the internal read and
write pointers are set to the first location of the RAM array, PAE goes
LOW, PAF goes HIGH, and HF goes HIGH.
mode or First Word Fall Through, that mode will remain selected. If the
IDT Standard mode is active, then FF will go HIGH and EF will go
LOW. If the First Word Fall Through mode is active, then OR will go
HIGH, and IR will go LOW.
unchanged. The programming method (parallel or serial) currently ac-
tive at the time of Partial Reset is also retained. The output register is
initialized to all zeroes. PRS is asynchronous.
operation, when reprogramming partial flag offset settings may not be
convenient.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
Data inputs for 9-bit wide data.
A Master Reset is accomplished whenever the MRS input is taken to
If LD is LOW during Master Reset, then PAE is assigned a threshold
Parallel reading of the registers is always permitted. (See section
During a Master Reset, the output register is initialized to all zeroes.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is taken to
Whichever mode is active at the time of Partial Reset, IDT Standard
Following Partial Reset, all values held in the offset registers remain
A Partial Reset is useful for resetting the device during the course of
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
If LD is HIGH during Master Reset, then PAE is assigned a thresh-
If FWFT is LOW during Master Reset then the IDT Standard mode,
0
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8
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RETRANSMIT (RT)
be accessed again. There are two stages: first, a setup procedure that
resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting
at the beginning of the memory.
edge. REN and WEN must be HIGH before bringing RT LOW.
the Retransmit setup by setting EF LOW. The change in level will only
be noticeable if EF was HIGH before setup.
internal read pointer is initialized to the first location of the RAM array.
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode),
for the relevant timing diagram.
Retransmit setup by setting OR HIGH. During this period, the internal
read pointer is set to the first location of the RAM array.
time, the contents of the first location appear on the outputs. Since
FWFT mode is selected, the first word appears on the outputs, no LOW
on REN is necessary. Reading all subsequent words requires a LOW
on REN to enable the rising edge of RCLK. See Figure 12, Retransmit
Timing (FWFT Mode), for the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
FWFT/SI input determines whether the device will operate in IDT Stan-
dard mode or First Word Fall Through (FWFT) mode. If, at the time of
Master Reset, FWFT/SI is LOW, then IDT Standard mode will be se-
lected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO memory. It also uses the Full
Flag function (FF) to indicate whether or not the FIFO memory has any
free space for writing.
first, must be requested using the Read Enable (REN) and RCLK.
will be selected. This mode uses Output Ready (OR) to indicate whether
or not there is valid data at the data outputs (Q
Ready (IR) to indicate whether or not the FIFO memory has any free
space for writing. In the FWFT mode, the first word written to an empty
FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is
n
necessary. Subsequent words must be accessed using the Read En-
able (REN) and RCLK.
and PAF offsets into the programmable registers. The serial input
function can only be used when the serial loading method has been
selected during Master Reset. Serial programming using the FWFT/SI
pin functions the same way in both IDT Standard and FWFT modes.
The Retransmit operation allows data that has already been read to
Retransmit setup is initiated by holding RT LOW during a rising RCLK
If IDT Standard mode is selected, the FIFO will mark the beginning of
When EF goes HIGH, Retransmit setup is complete and read opera-
If FWFT mode is selected, the FIFO will mark the beginning of the
When OR goes LOW, Retransmit setup is complete; at the same
This is a dual purpose pin. During Master Reset, the state of the
In IDT Standard mode, every word read from the FIFO, including the
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode
After Master Reset, FWFT/SI acts as a serial input for loading PAE
COMMERCIAL AND INDUSTRIAL
o
TEMPERATURE RANGES
During this period, the
JANUARY 30, 2009
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