S25FL128P0XMFI001 Spansion Inc., S25FL128P0XMFI001 Datasheet - Page 35

• Manufacturer Part Number: S25FL128P0XMFI001
• Description: IC, FLASH, 128MBIT, 104MHZ, SOIC-16
• Manufacturer: Spansion Inc.

Specifications of S25FL128P0XMFI001

• Memory Type: Flash
• Memory Size: 128Mbit
• Ic Interface Type: Serial, SPI
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: SOIC
• No. Of Pins: 16
• Data Bus Width: 1 bit
• Architecture: Uniform
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 26 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: SO-16
• Cell Type: NOR
• Density: 128Mb
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 1b
• Number Of Words: 128Mword
• Supply Current: 22mA
• Mounting: Surface Mount
• Pin Count: 16
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.12 Deep Power Down (DP: B9h)
September 8, 2009 S25FL128P_00_08
The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is
intended for periods when the device is not in active use, and ignores all commands except for the Release
from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection
against unintended write operations. The standard standby mode, which the device goes into automatically
when CS# is high (and all operations in progress are complete), should generally be used for the lowest
power consumption when the quickest return to device activity is required.
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the
entire duration of the DP sequence. The command sequence is shown in
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise
the device does not execute the command. After a delay of t
reduces from I
Once the device has entered the DP mode, all commands are ignored except the RES command (which
releases the device from the DP mode). The RES command also provides the Electronic Signature of the
device to be output on SO, if desired (see sections
DP mode automatically terminates when power is removed, and the device always powers up in the standard
standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write
Status Register operation, and continues the operation uninterrupted.
SO/PO[7-0]
SCK
CS#
SI
SB
Hi-Z
Mode 3
Mode 0
to I
DP
(see
Figure 11.18 Deep Power Down (DP) Command Sequence
D a t a
Table 17.1 on page
0
S h e e t
1
S25FL128P
2
Command
3
41).
4
11.13
5
and 11.14).
Standby Mode
6
DP,
7
the device enters the DP mode and current
t DP
Figure 11.18
Deep Power-down Mode
and
Table
11.6.
35