S25FL128P0XMFI001 Spansion Inc., S25FL128P0XMFI001 Datasheet - Page 37

• Manufacturer Part Number: S25FL128P0XMFI001
• Description: IC, FLASH, 128MBIT, 104MHZ, SOIC-16
• Manufacturer: Spansion Inc.

Specifications of S25FL128P0XMFI001

• Memory Type: Flash
• Memory Size: 128Mbit
• Ic Interface Type: Serial, SPI
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: SOIC
• No. Of Pins: 16
• Data Bus Width: 1 bit
• Architecture: Uniform
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 26 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: SO-16
• Cell Type: NOR
• Density: 128Mb
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 1b
• Number Of Words: 128Mword
• Supply Current: 22mA
• Mounting: Surface Mount
• Pin Count: 16
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Notes
1. In parallel mode, the maximum access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
2. To release the device from Deep Power Down and read Electronic ID in parallel mode, a Parallel Mode Enter command (55h) must be issued before the RES
3. Byte 1 will output the Electronic Signature.
September 8, 2009 S25FL128P_00_08
11.14.2
command. The device will not exit parallel mode until a Parallel Mode Exit command (45h) is written, or upon power-down or power-up sequence.
SCK
CS#
PO[7-0]
SO
SI
SCK
CS#
SI
Hi-Z
Hi-Z
Parallel Mode
When the device is in parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a
single clock cycle instead of eight clock cycles to access the next data byte. The method of memory content
output will be the same compared to outside of parallel mode. The only difference is that a byte of data is
output per clock cycle instead of a single bit. In this case, the Electronic Signature will be output onto the
P0[7–0] parallel output pins.
0
1
0
2
1
Command
2
Figure 11.21 Parallel Release from Deep Power Down and
3
Figure 11.20 Serial Release from Deep Power Down and
Command
Read Electronic Signature (RES) Command Sequence
Read Electronic Signature (RES) Command Sequence
3
4
5
4
D a t a
6
5
7
6
MSB
23 22 21
8
7
MSB
23 22 21
9 10
8
S h e e t
3 Dummy Bytes
9 10
S25FL128P
3 Dummy Bytes
Electronic ID
28 29 30 31 32 33 34 35 36 37 38
3 2
Deep Power-down Mode
28 29 30 31 32 33 34 35 36 37 38
3 2
Deep Power-down Mode
1
0
1
MSB
7
0
Byte
1
6
5
Electronic ID out
4
3
2
1
0
t
RES
t
RES
Standby Mode
Standby Mode
37