S29AL032D90TFI000 Spansion Inc., S29AL032D90TFI000 Datasheet - Page 2

• Manufacturer Part Number: S29AL032D90TFI000
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL032D90TFI000

• Memory Size: 32Mbit
• Memory Configuration: 4M X 8
• Ic Interface Type: CFI, Parallel
• Access Time: 90ns
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: TSOP
• No. Of Pins: 40
• Memory Type: Uniform Sector Flash
• Interface Type: CFI
• Rohs Compliant: Yes
• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 90ns
• Boot Type: Top
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

S29AL032D Features
2
The S29AL032D is a 32 Mbit, 3.0 volt-only Flash memory organized as 4,194,304 bytes or
2,097,152 words. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. To eliminate bus contention, the device has separate chip
enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase
operations. No VPP is required for program or erase operations. The device can also be
programmed in standard EPROM programmers.
The device is entirely command set compatible with the JEDEC single-power-supply
Flash standard. Commands are written to the command register using standard
microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates
the Embedded Program algorithm—an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates
faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase algorithm—an internal algorithm that automatically preprograms the
array (if it is not already programmed) before executing the erase operation. During erase,
the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing
the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After
a program or erase cycle is completed, the device is ready to read array data or accept
another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed
without affecting the data contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low V
write operations during power transitions. The hardware sector protection feature
disables both program and erase operations in any combination of the sectors of memory.
This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is not selected for erasure. True
background erase can thus be achieved.
The hardware RESET# input terminates any operation in progress and resets the internal
state machine to reading array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified
amount of time, the device enters the automatic sleep mode. The system can also place
the device into the standby mode. Power consumption is greatly reduced in both these
modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience
to produce the highest levels of quality, reliability and cost effectiveness. The device
electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
S29AL032D Known Good Die
S u p p l e m e n t
CC
S29AL032D_KGD_SP_02 July 18, 2007
detector that automatically inhibits