AM29F800BB-55SF Spansion Inc., AM29F800BB-55SF Datasheet - Page 17
![IC, FLASH, 8MBIT, 55NS, SOIC-44](/photos/19/5/190559/4243291_sml.jpg)
AM29F800BB-55SF
Manufacturer Part Number
AM29F800BB-55SF
Description
IC, FLASH, 8MBIT, 55NS, SOIC-44
Manufacturer
Spansion Inc.
Datasheet
1.AM29F800BB-55SF.pdf
(45 pages)
Specifications of AM29F800BB-55SF
Memory Type
Flash
Memory Size
8Mbit
Memory Configuration
1M X 8 / 512K X 16
Access Time
55ns
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
44
Cell Type
NOR
Density
8Mb
Access Time (max)
55ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
20/19Bit
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
SO
Program/erase Volt (typ)
4.5 to 5.5V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
50mA
Mounting
Surface Mount
Pin Count
44
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AM29F800BB-55SF
Manufacturer:
AMD
Quantity:
1 200
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires V
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is un-
protected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically provides internally gen-
erated program pulses and verify the programmed cell
margin. The Command Definitions take shows the ad-
dress and data requirements for the byte program com-
mand sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
August 3, 2009 21504E7
ID
on address bit A9.
D A T A S H E E T
Am29F800B
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note: See the appropriate Command Definitions table for
program command sequence.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Increment Address
Figure 2. Program Operation
in progress
Embedded
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
No
15