IS61NLP25636A-200TQLI INTEGRATED SILICON SOLUTION (ISSI), IS61NLP25636A-200TQLI Datasheet

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IS61NLP25636A-200TQLI

Manufacturer Part Number
IS61NLP25636A-200TQLI
Description
IC, SRAM, 9MBIT, 3.1NS, TQFP-100
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS61NLP25636A-200TQLI

Memory Size
9Mbit
Memory Configuration
256K X 8
Clock Frequency
200MHz
Access Time
3.1ns
Supply Voltage Range
3.135V To 3.465V
Memory Case Style
TQFP
No. Of Pins
100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61NLP25636A-200TQLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61NLP25636A-200TQLI
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS61NLP25636A-200TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
256K x 36 and 512K x 18
9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
• Interleaved or linear burst sequence control us-
• Three chip enables for simple depth expansion
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and
• Power supply:
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. G
07/28/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
data and control
ing MODE input
and address pipelining
119-ball PBGA packages
NVP: V
NLP: V
Symbol
t
t
kq
kc
dd
dd
3.3V (± 5%), V
2.5V (± 5%), V
Parameter
Clock Access Time
Cycle Time
Frequency
ddq
ddq
3.3V/2.5V (± 5%)
2.5V (± 5%)
-250
250
2.6
4
1-800-379-4774
DESCRIPTION
The 9 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
device will hold their previous values.
All Read,Write and Deselect cycles are initiated by the ADV
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
sequence.When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
A burst mode pin (MODE) defines the order of the burst
-200
200
3.1
5
ISSI
Units
MHz
ns
ns
's advanced CMOS technology.
JULY 2010
1

Related parts for IS61NLP25636A-200TQLI

IS61NLP25636A-200TQLI Summary of contents

Page 1

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • ...

Page 2

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A BLOCK DIAGRAM x 36: A [0:17] or ADDRESS x 18: A [0:18] REGISTER CLK CONTROL LOGIC K CKE CE CE2 CE2 CONTROL } ADV REGISTER WE BWŸ X (X=a,b,c DQx/DQPx 2 A2-A17 or A2-A18 MODE BURST ADDRESS A0-A1 A'0-A'1 COUNTER WRITE WRITE ADDRESS ADDRESS REGISTER REGISTER CONTROL LOGIC Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 3

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A Bottom View 119-Ball BGA 1 mm Ball Pitch Ball Array Integrated Silicon Solution, Inc. — www.issi.com — Rev. G 07/28/2010 Bottom View 165-Ball 15mm BGA 1 mm Ball Pitch Ball Array 1-800-379-4774 3 ...

Page 4

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A PIN CONFIGURATION — 256K CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq G DQc DQc V ddq DQd DQd V ddq K DQd DQd V ddq L DQd DQd V ddq M DQd DQd V ddq N DQPd NC V ddq MODE NC A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 119-PIN PBGA PACKAGE CONFIGURATION DDQ B NC CE2 NC C DQc DQPc D DQc DQc E V DQc F DDQ DQc DQc G H DQc DQc DDQ K DQd DQd L DQd DQd V DQd M DDQ DQd DQd N DQd DQPd TMS DDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 6

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 165-PIN PBGA PACKAGE CONFIGURATION CE2 DDQ DQb DDQ V DQb E NC DDQ DQb DDQ V DDQ G NC DQb DDQ DQb DQb DDQ DQb DDQ V M DQb NC DDQ NC N DQPb V DDQ MODE Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 119-PIN PBGA PACKAGE CONFIGURATION DDQ B NC CE2 DQb D E DQb DDQ NC DQb G H DQb DDQ K DQb NC L DQb DQb DDQ DQb DQPb TMS DDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A PIN CONFIGURATION 100-Pin TQFP 100 DQPc 1 2 DQc 3 DQc 4 V DDQ 5 Vss 6 DQc 7 DQc 8 DQc 9 DQc 10 Vss 11 V DDQ 12 DQc 13 DQc Vss 18 DQd 19 DQd 20 V DDQ 21 Vss 22 DQd 23 DQd 24 DQd 25 DQd Vss DDQ 28 DQd 29 DQd DQPd 256K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A STATE DIAGRAM BEGIN READ READ READ BURST BURST BURST READ SYNCHRONOUS TRUTH TABLE Address Operation Used Not Selected N/A Not Selected N/A Not Selected N/A Not Selected Continue N/A Begin Burst Read External Address Continue Burst Read Next Address ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H Read L L Write L Deselected L Notes means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A WRITE TRUTH TABLE (x36) Operation WE READ H WRITE BYTE a L WRITE BYTE b L WRITE BYTE c L WRITE BYTE d L WRITE ALL BYTEs L WRITE ABORT/NOP L Notes : 1. X means "Don't Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK. ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A LINEAR BURST ADDRESS TABLE A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation d I Output Current (per I/O) ouT Voltage Relative ouT V Voltage Relative for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions V Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Ih V Input LOW Voltage Il I Input Leakage Current Output Leakage Current V lo POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I AC Operating Device Selected ≤ V ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A CAPACITANCE (1,2) Symbol Parameter c Input Capacitance In c Input/Output Capacitance ouT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 Integrated Silicon Solution, Inc. — www.issi.com — ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ t Clock High to Output High-Z ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SLEEP MODE active to input ignored PdS t ZZ inactive to input sampled PuS t ZZ active to SLEEP current ZZI t ZZ inactive to exit SLEEP current rZZI SLEEP MODE TIMING CLK t PDS ZZ setup cycle ZZ t ZZI ...

Page 18

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A READ CYCLE TIMING CLK t t ADVS ADVH ADV Address WRITE CKE t t CES CEH OEQ t OEHZ Data Out Q1-1 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...

Page 19

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A WRITE CYCLE TIMING t KH CLK t KC ADV Address A1 A2 WRITE CKE CE OE Data In D1-1 t OEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...

Page 20

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A SINGLE READ/WRITE CYCLE TIMING CLK CKE Address WRITE CE ADV OE t OEQ t OELZ Data Out Q1 Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 21

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A CKE OPERATION TIMING CLK CKE Address A1 A2 WRITE CE ADV OE Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 22

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A CE OPERATION TIMING CLK CKE A1 A2 Address WRITE CE ADV OE t OEQ t OELZ Q1 Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = KQHZ KQ t KQLZ Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 23

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61NLP and IS61NVP have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in ac- cordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. ...

Page 24

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers.The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...

Page 25

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149 ...

Page 26

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be- tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO ...

Page 27

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage oh1 V Output HIGH Voltage oh2 V Output LOW Voltage ol1 V Output LOW Voltage ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Leakage Current x Notes: 1. All Voltage referenced to Ground. ...

Page 28

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMING 1 t THTH TCK t MVTH TMS t DVTH TDI TDO 28 TAP Output Load Equivalent 1ns 1 ...

Page 29

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 165 PBGA BOUNDARY SCAN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa 11L 34 15 DQa 11K 35 16 DQa 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 ...

Page 30

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 119 BGA BOUNDARY SCAN ORDER (x 36) 30 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/28/2010 ...

Page 31

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 165 PBGA BOUNDARY SCAN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 32

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 119 BGA BOUNDARY SCAN ORDER (x 18) 32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/28/2010 ...

Page 33

... IS61NLP25636A-250B3 IS61NLP25636A-250B2 IS61NLP25636A-200TQ IS61NLP25636A-200B3 IS61NLP25636A-200B2 512Kx18 IS61NLP51218A-250TQ IS61NLP51218A-250B3 IS61NLP51218A-250B2 IS61NLP51218A-200TQ IS61NLP51218A-200B3 IS61NLP51218A-200B2 Order Part Number 256Kx36 IS61NLP25636A-250TQI IS61NLP25636A-250B3I IS61NLP25636A-250B2I IS61NLP25636A-200TQI IS61NLP25636A-200TQLI IS61NLP25636A-200B3I IS61NLP25636A-200B3LI IS61NLP25636A-200B2I IS61NLP25636A-200B2LI 512Kx18 IS61NLP51218A-250TQI IS61NLP51218A-250B3I IS61NLP51218A-250B2I IS61NLP51218A-200TQI IS61NLP51218A-200TQLI IS61NLP51218A-200B3I IS61NLP51218A-200B2I 1-800-379-4774 Package 100 TQFP 165 PBGA 119 PBGA ...

Page 34

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Access Time 250 200 250 200 Industrial Range: -40°C to +85°C Access Time 250 200 250 200 34 = 2.5V/V = 2.5V) DD DDq Order Part Number 256Kx36 IS61NVP25636A-250TQ IS61NVP25636A-250B3 IS61NVP25636A-250B2 IS61NVP25636A-200TQ IS61NVP25636A-200B3 IS61NVP25636A-200B2 512Kx18 IS61NVP51218A-250TQ ...

Page 35

... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A Integrated Silicon Solution, Inc. — www.issi.com — Rev. G 07/28/2010 1-800-379-4774 35 ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 36 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/28/2010 ...

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... IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A Integrated Silicon Solution, Inc. — www.issi.com — Rev. G 07/28/2010 1-800-379-4774 37 ...

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