PIC24FJ256GB210-I/BG Microchip Technology, PIC24FJ256GB210-I/BG Datasheet - Page 378

• Manufacturer Part Number: PIC24FJ256GB210-I/BG
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, BGA-121
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB210-I/BG

• Controller Family/series: PIC24
• No. Of I/o's: 84
• Ram Memory Size: 96KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 9
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 5
• Operating Supply Voltage: 2.2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240021
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GB210 FAMILY
CPU
CRC
CTMU
Customer Change Notification Service ............................. 382
Customer Notification Service........................................... 382
Customer Support ............................................................. 382
D
Data Memory
DC Characteristics
Development Support ....................................................... 335
Device Features
Doze Mode........................................................................ 150
E
Electrical Characteristics
Enhanced Parallel Master Port. See EPMP...................... 269
ENVREG Pin..................................................................... 330
EPMP ................................................................................ 269
Equations
DS39975A-page 378
Arithmetic Logic Unit (ALU)......................................... 41
Control Registers ........................................................ 40
Core Registers ............................................................ 38
Programmer’s Model................................................... 37
32-Bit Programmable Cyclic Redundancy Check ..... 293
Polynomials............................................................... 294
Setup Examples for 16 and 32-Bit Polynomials ........ 294
User Interface ........................................................... 294
Measuring Capacitance ............................................ 319
Measuring Time ........................................................ 320
Pulse Generation and Delay ..................................... 320
Address Space............................................................ 45
Extended Data Space (EDS) ...................................... 68
Memory Map ............................................................... 46
Near Data Space ........................................................ 47
SFR Space.................................................................. 47
Software Stack ............................................................ 72
Space Organization, Alignment .................................. 47
I/O Pin Input Specifications ....................................... 353
I/O Pin Output Specifications .................................... 354
Idle Current ............................................................... 351
Operating Current ..................................................... 350
Program Memory ...................................................... 354
Temperature and Voltage Specifications .................. 349
Thermal Conditions ................................................... 348
Voltage Regulator Specifications .............................. 355
100/121--Pin ............................................................... 18
64-Pin.......................................................................... 17
Absolute Maximum Ratings ...................................... 347
V/F Graph ................................................................. 348
ALTPMP Setting ....................................................... 269
Key Features............................................................. 269
Master Port Pins ....................................................... 270
16-Bit, 32-Bit CRC Polynomials ................................ 294
A/D Conversion Clock Period ................................... 308
Baud Rate Reload Calculation .................................. 219
Calculating the PWM Period ..................................... 198
Calculation for Maximum PWM Resolution............... 199
Estimating USB Transceiver Current
Relationship Between Device and SPI
RTCC Calibration ...................................................... 290
UART Baud Rate with BRGH = 0 ............................. 226
UART Baud Rate with BRGH = 1 ............................. 226
Consumption..................................................... 238
Clock Speed...................................................... 215
Errata .................................................................................. 14
Extended Data Space (EDS) ............................................ 269
F
Flash Configuration Words ......................................... 44, 323
Flash Program Memory ...................................................... 79
I
I/O Ports
I
Idle Mode .......................................................................... 150
Input Capture
Input Capture with Dedicated Timers ............................... 191
Input Voltage Levels for Port or Pin
Instruction Set
Instruction-Based Power-Saving Modes................... 149, 150
Interfacing Program and Data Spaces................................ 72
Inter-Integrated Circuit. See I
Internet Address ............................................................... 382
Interrupt Vector Table (IVT) ................................................ 91
Interrupts
J
JTAG Interface.................................................................. 333
K
Key Features .................................................................... 323
2
C
Enhanced ICSP Operation ......................................... 80
JTAG Operation.......................................................... 80
Programming Algorithm .............................................. 82
RTSP Operation ......................................................... 80
Single-Word Programming ......................................... 84
Table Instructions ....................................................... 79
Analog Port Pins Configuration................................. 152
Analog/Digital Function of an I/O Pin........................ 152
Input Change Notification ......................................... 157
Open-Drain Configuration......................................... 152
Parallel (PIO) ............................................................ 151
Peripheral Pin Select ................................................ 158
Pull-ups and Pull-Downs........................................... 157
Selectable Input Sources.......................................... 159
Write/Read Timing .................................................... 152
Clock Rates .............................................................. 219
Reserved Addresses ................................................ 219
Setting Baud Rate as Bus Master............................. 219
Slave Address Masking ............................................ 219
32-Bit Mode (Cascaded)........................................... 192
Operations ................................................................ 192
Synchronous and Trigger Modes.............................. 191
Tolerated Description Input....................................... 152
Opcode Symbols ...................................................... 340
Overview................................................................... 341
Summary .................................................................. 339
Control and Status Registers...................................... 94
Implemented Vectors.................................................. 93
Reset Sequence ......................................................... 91
Setup and Service Procedures ................................. 135
Trap Vector Details ..................................................... 92
Vector Table ............................................................... 92
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C. ...................................... 217