PIC16F1827-I/MQ Microchip Technology, PIC16F1827-I/MQ Datasheet - Page 177

• Manufacturer Part Number: PIC16F1827-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1827-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4 Kwords
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 384 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN EP
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / Rohs Status: Details

20.0
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 3-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP/ECCP)
• Selectable Gate Source Polarity
FIGURE 20-1:
© 2009 Microchip Technology Inc.
Asynchronous mode only)
SYNCC1OUT
Comparator 1
Comparator 2
SYNCC2OUT
From Timer0
T1G
Overflow
T1GSS<1:0>
Note 1: ST Buffer is high speed type when using T1CKI.
TIMER1 MODULE WITH GATE
CONTROL
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
T1OSCEN
T1OSO
T1GPOL
T1CKI
T1OSI
Set flag bit
TMR1IF on
Overflow
00
10
11
TIMER1 BLOCK DIAGRAM
01
TMR1ON
T1GTM
T1OSC
TMR1H
EN
OUT
TMR1
(1)
T1G_IN
(2)
D
R
CK
TMR1L
Q
Q
1
0
Preliminary
TMR1CS<1:0>
Cap. Sensing
0
1
Oscillator
T1GGO/DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
D
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
• Gate Event Interrupt
Figure 20-1 is a block diagram of the Timer1 module.
Single Pulse
Acq. Control
T1CLK
11
10
01
00
T1GSPM
PIC16F/LF1826/27
T1CKPS<1:0>
T1SYNC
Prescaler
1, 2, 4, 8
TMR1ON
0
1
To Clock Switching Modules
2
0
1
Internal
F
Clock
T1GVAL
OSC
TMR1GE
/2
Q1
Synchronized
Synchronize
Interrupt
clock input
D
EN
det
det
Sleep input
Q
(3)
To Comparator Module
DS41391B-page 177
Set
TMR1GIF
T1GCON
Data Bus
RD