PIC24HJ256GP210A-I/PF Microchip Technology, PIC24HJ256GP210A-I/PF Datasheet - Page 28

• Manufacturer Part Number: PIC24HJ256GP210A-I/PF
• Description: IC, 16BIT MCU, PIC24H, 40MIPS, TQFP-100
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP210A-I/PF

• Controller Family/series: PIC24
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 9
• Interface: I2C, LIN, SPI, UART
• No. Of Pwm Channels: 8
• Core Size: 16 Bit
• Program Memory Size: 256 KB
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Embedded Interface Type: I2C, LIN, SPI, UART
• Rohs Compliant: Yes
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2.10
The ERASEP command instructs the programming
executive to page erase [NUM_PAGES] of code mem-
ory. The code memory must be erased at an “even” 512
instruction word address boundary
Expected Response (2 words):
0x1900
0x0002
DS70152H-page 28
Opcode
Length
NUM_PAGES Up to 255
Addr_MSB
Addr_LS
15
Opcode
Field
NUM_PAGES
ERASEP
12 11
0x9
0x3
Most Significant Byte of the 24-bit
address
Least Significant 16 bits of the 24-bit
address
COMMAND
Addr_LS
8 7
Description
Length
Addr_MSB
0
4.2.11
The CRCP command performs a CRC-16 on the range
of memory specified. This command can substitute for
a full chip verify. Data is shifted in a packed method as
demonstrated
Significant Byte first.
Example:
CRC-CITT-16 with test data of “123456789” becomes
0x29B1
Expected Response (3 words):
QE_Code: 0x1C00
Length: 0x0003
CRC Value: 0xXXXX
Opcode
Length
Reserved
Addr_MSB
Addr_LSW
Size
15
Opcode
Field
Reserved
Reserved
CRCP
12 11
0xC
0x5
0x0
Most Significant Byte of 24-bit
address
Least Significant 16 bits of 24-bit
address
Number of 24-bit locations (address
range divided by 2)
in
COMMAND
Addr_LSW
Size_LSW
Figure
© 2010 Microchip Technology Inc.
8 7
Description
4-4,
Length
byte-wise
Addr_MSB
Size_MSB
Least
0