PIC24HJ256GP210A-I/PF Microchip Technology, PIC24HJ256GP210A-I/PF Datasheet - Page 36

• Manufacturer Part Number: PIC24HJ256GP210A-I/PF
• Description: IC, 16BIT MCU, PIC24H, 40MIPS, TQFP-100
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP210A-I/PF

• Controller Family/series: PIC24
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 9
• Interface: I2C, LIN, SPI, UART
• No. Of Pwm Channels: 8
• Core Size: 16 Bit
• Program Memory Size: 256 KB
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Embedded Interface Type: I2C, LIN, SPI, UART
• Rohs Compliant: Yes
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 5-1:
DS70152H-page 36
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
R/SO-0
Note 1: These bits can only be reset on a Power-on Reset (POR).
WR
U-0
—
2: All other combinations of NVMOP<3:0> are unimplemented.
(1)
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
If ERASE = 1:
1111 = Memory Bulk Erase operation
1110 = Reserved
1101 = Erase General Segment
1100 = Erase Secure Segment
1011 = Reserved
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte
If ERASE = 0:
1111 = No operation
1110 = Reserved
1101 = No operation
1100 = No operation
1011 = Reserved
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
R/W-0
R/W-0
ERASE
WREN
cleared by hardware once operation is complete
automatically on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
(1)
SO = Satiable only bit
‘1’ = Bit is set
W = Writable bit
R/W-0
WRERR
U-0
—
(1)
U-0
U-0
—
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
(1)
R/W-0
U-0
—
NVMOP<3:0>
(1)
© 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
(2)
—
(1)
R/W-0
U-0
—
(1)
bit 8
bit 0