PIC24HJ256GP210A-I/PF Microchip Technology, PIC24HJ256GP210A-I/PF Datasheet - Page 80

• Manufacturer Part Number: PIC24HJ256GP210A-I/PF
• Description: IC, 16BIT MCU, PIC24H, 40MIPS, TQFP-100
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP210A-I/PF

• Controller Family/series: PIC24
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 9
• Interface: I2C, LIN, SPI, UART
• No. Of Pwm Channels: 8
• Core Size: 16 Bit
• Program Memory Size: 256 KB
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Embedded Interface Type: I2C, LIN, SPI, UART
• Rohs Compliant: Yes
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Revision F (March 2008)
• Removed Preliminary status from document
• Added information specific to the following new
• Added a Note to
• Added BOREN bit (FPOR<3>) to Configuration
• Updated Note 1 in
• Updated Note in
• Updated Figure 5-2
• Added Register 5-1
• Updated Table 5-7 and Table 5-8
• Added
DS70152H-page 80
- dsPIC33FJ06GS101
- dsPIC33FJ06GS102
- dsPIC33FJ06GS202
- dsPIC33FJ16GS402
- dsPIC33FJ16GS404
- dsPIC33FJ16GS502
- dsPIC33FJ16GS504
- dsPIC33FJ32GP302
- dsPIC33FJ32GP304
- dsPIC33FJ32MC302
- dsPIC33FJ32MC304
- dsPIC33FJ64GP202
- dsPIC33FJ64GP204
- dsPIC33FJ64GP802
- dsPIC33FJ64GP804
- dsPIC33FJ64MC202
- dsPIC33FJ64MC204
- dsPIC33FJ64MC802
- dsPIC33FJ64MC804
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devices in several sections, including program
memory sizes, Configuration bit descriptions,
checksum computations, Configuration registers
and Device ID values:
Write/Erase Requirements”
eight instruction words of test memory for
dsPIC33FJX6GSXXX devices)
Register Map and added Note 5 (see Table 3-4)
Instruction Execution”
Instruction Execution”
Errata Addendum”
Appendix B: “Device ID Register Silicon
Section 2.2 “Program Memory
Section 5.3.2 “REGOUT Serial
Section 5.3.1 “SIX Serial
- dsPIC33FJ128GP202
- dsPIC33FJ128GP204
- dsPIC33FJ128GP802
- dsPIC33FJ128GP804
- dsPIC33FJ128MC202
- dsPIC33FJ128MC204
- dsPIC33FJ128MC802
- dsPIC33FJ128MC804
- PIC24HJ32GP302
- PIC24HJ32GP304
- PIC24HJ64GP202
- PIC24HJ64GP204
- PIC24HJ64GP502
- PIC24HJ64GP504
- PIC24HJ128GP202
- PIC24HJ128GP204
- PIC24HJ128GP502
- PIC24HJ128GP504
(preserving last
Revision G (March 2009)
This revision includes minor updates to the text such as
typographical errors, formatting and grammar.
The following detail the major updates:
• Added
• Reordered the appendixes so that the Revision
• Updated all occurrences of V
• Updated all occurrences of PGCn and PGDn
• Added information specific to the following new
• Moved Note from
• Added Note 2 to
• Changed the user memory limit for
• Changed the Configuration Register ending
- dsPIC33FJ64GP206A
- dsPIC33FJ64GP306A
- dsPIC33FJ64GP310A
- dsPIC33FJ64GP706A
- dsPIC33FJ64GP708A
- dsPIC33FJ64GP710A
- dsPIC33FJ64MC506A
- dsPIC33FJ64MC508A
- dsPIC33FJ64MC510A
- dsPIC33FJ64MC706A
- dsPIC33FJ64MC710A
- PIC24HJ64GP206A
- PIC24HJ64GP210A
- PIC24HJ64GP506A
- PIC24HJ64GP510A
- dsPIC33FJ128GP206A
- dsPIC33FJ128GP306A
- dsPIC33FJ128GP310A
- dsPIC33FJ128GP706A
- dsPIC33FJ128GP708A
- dsPIC33FJ128GP710A
- dsPIC33FJ128MC506A
- dsPIC33FJ128MC510A
- dsPIC33FJ128MC706A
Calibration Registers”
History appears last in the document
V
(where n = 1, 2 or 3) to PGECn and PGDn,
respectively
devices in several sections, including
Configuration bit descriptions, checksum
computations, Configuration registers and Device
ID values:
Memory Write/Erase Requirements”
Section 5.0 “Device Programming – ICSP”
dsPIC33FJ16GS402/404/502/504 devices to
0x002BFE in
address to 0xF80016 in
DDCORE
Appendix C: “Diagnostic and
Table 2-2
Figure 2-2
Section 2.2 “Program
© 2010 Microchip Technology Inc.
Figure 2-3
- dsPIC33FJ128MC708A
- dsPIC33FJ128MC710A
- PIC24HJ128GP206A
- PIC24HJ128GP210A
- PIC24HJ128GP306A
- PIC24HJ128GP310A
- PIC24HJ128GP506A
- PIC24HJ128GP510A
- dsPIC33FJ256GP506A
- dsPIC33FJ256GP510A
- dsPIC33FJ256GP710A
- dsPIC33FJ256MC510A
- dsPIC33FJ256MC710A
- PIC24HJ256GP206A
- PIC24HJ256GP210A
- PIC24HJ256GP610A
- dsPIC33FJ32GS406
- dsPIC33FJ32GS606
- dsPIC33FJ32GS608
- dsPIC33FJ32GS610
- dsPIC33FJ64GS406
- dsPIC33FJ64GS606
- dsPIC33FJ64GS608
- dsPIC33FJ64GS610
DDCORE
to V
to
CAP
/