AT80C51RD2-SLSUM Atmel, AT80C51RD2-SLSUM Datasheet - Page 17

• Manufacturer Part Number: AT80C51RD2-SLSUM
• Description: MCU, 8BIT, 8051, 5V, SPI, 20MHZ, 44PLCC
• Manufacturer: Atmel

Specifications of AT80C51RD2-SLSUM

• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Core Size: 8bit
• Oscillator Type: External Only
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1
4188F–8051–01/08
Expanded RAM (XRAM)
The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for
increased data parameter handling and high level language usage.
RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external
data space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data
space.
The TS80C51Rx2 has internal data memory that is mapped into four separate segments.
The four segments are:
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. That means they have the same address, but are physically sepa-
rate from SFR space.
When an instruction accesses an internal location above address 7FH, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction.
• 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly
• 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
• 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable
• 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, #
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
• The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bit
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.
addressable.
only.
EXTRAM bit cleared in the AUXR register. (See Table 6-1.)
data, accesses the SFR at location 0A0H (which is P2).
example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address
0A0H, rather than P2 (whose address is 0A0H).
cleared and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first 256 or 768 bytes of external data memory.
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM
= 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H
rather than external memory. An access to external data memory locations higher than FFH
(i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be
performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so
with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals.
Refer to Figure 6-1. For RD devices, accesses to expanded RAM from 100H to 2FFH can
only be done thanks to the use of DPTR.
MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output
port pins can be used to output higher order address bits. This is to provide the external
paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-
order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight
AT/TS8xC51Rx2
17