AT80C51RD2-SLSUM Atmel, AT80C51RD2-SLSUM Datasheet - Page 46

• Manufacturer Part Number: AT80C51RD2-SLSUM
• Description: MCU, 8BIT, 8051, 5V, SPI, 20MHZ, 44PLCC
• Manufacturer: Atmel

Specifications of AT80C51RD2-SLSUM

• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Core Size: 8bit
• Oscillator Type: External Only
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.8
6.8.1
46
Hardware Watchdog Timer
AT/TS8xC51Rx2
Using the WDT
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is no way
to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-
tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
1/F
will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
ranking from 16ms to 2s @ F
description,
Table 6-21.
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
Table 6-22.
Reset value
OSC
T4
7
. To make the best use of the WDT, it should be serviced in those sections of code that
Table 6-22
WDTRST Register
WDTRST Address (0A6h)
WDTPRG Register
WDTPRG Address (0A7h)
T3
6
X
7
(SFR0A7h).
T2
5
OSC
X
6
= 12MHz. To manage this feature, refer to WDTPRG register
7
counter has been added to extend the Time-out capability,
X
5
T1
4
4
X
T0
3
X
3
S2
2
X
2
OSC
S1
1
, where T
4188F–8051–01/08
X
1
S0
0
OSC
=