COP8SGE744V8 National Semiconductor, COP8SGE744V8 Datasheet - Page 31

• Manufacturer Part Number: COP8SGE744V8
• Description: IC, 8BIT MCU, COP8, 15MHZ, LCC-44
• Manufacturer: National Semiconductor

Specifications of COP8SGE744V8

• Controller Family/series: COP8
• No. Of I/o's: 40
• Ram Memory Size: 256Byte
• Cpu Speed: 15MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 6
• Digital Ic Case Style: LCC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: SPI, USART
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.0 USART
8.6 USART INTERRUPTS
The USART is capable of generating interrupts. Interrupts
are generated on Receive Buffer Full and Transmit Buffer
Empty. Both interrupts have individual interrupt vectors. Two
bytes of program memory space are reserved for each in-
terrupt vector. The two vectors are located at addresses
0xEC to 0xEF Hex in the program memory space. The
interrupts can be individually enabled or disabled using En-
able Transmit Interrupt (ETI) and Enable Receive Interrupt
(ERI) bits in the ENUI register.
The interrupt from the Transmitter is set pending, and re-
mains pending, as long as both the TBMT and ETI bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).
The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and ERI bits are set. To
remove this interrupt, software must either clear the ERI bit
or read from the RBUF register (thus clearing the RBFL bit).
8.7 Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the USART can be individually selected to come either from
an external source at the CKX pin (port L, pin L1) or from a
(Continued)
FIGURE 22. Framing Formats
31
source selected in the PSR and BAUD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1–16 (in-
crements of 0.5) prescaler and an 11-bit binary counter.
( Figure 23 ). The divide factors are specified through two
read/write registers shown in Figure 24 . Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Reg-
ister (PSR). PSR is cleared upon reset.
As shown in Table 5 , a Prescaler Factor of 0 corresponds to
NO CLOCK. This condition is the USART power down mode
where the USART clock is turned off for power saving pur-
pose. The user must also turn the USART clock off when a
different baud rate is chosen.
The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table 5 . There are many
ways to calculate the two divisor factors, but one particularly
effective method would be to achieve a 1.8432 MHz fre-
quency coming out of the first stage. The 1.8432 MHz pres-
caler output is then used to drive the software programmable
baud rate counter to create a 16x clock for the following baud
rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600,
4800, 7200, 9600, 19200 and 38400 ( Table 4 ). Other baud
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