PIC16F1826-I/MQ Microchip Technology, PIC16F1826-I/MQ Datasheet - Page 110

• Manufacturer Part Number: PIC16F1826-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1826-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 2kWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1826/27
11.1.4
To read a program memory location, the user must:
1.
2.
3.
4.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF EECON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the EEDATL and EEDATH registers; therefore, it can
be read as two bytes in the following instructions.
EXAMPLE 11-3:
DS41391B-page 110
;
Write the Least and Most Significant address
bits to the EEADRL and EEADRH registers.
Clear the CFGS bit of the EECON1 register.
Set the EEPGD control bit of the EECON1
register.
Then, set control bit RD of the EECON1 register.
BANKSEL EEADRL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL EECON1
BSF
BSF
NOP
NOP
BANKSEL EEDATL
MOVF
MOVWF
MOVF
MOVWF
READING THE FLASH PROGRAM
MEMORY
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADRL
EECON1, EEPGD
EECON1, RD
EEDATL, W
LOWPMBYTE
EEDATH, W
HIGHPMBYTE
FLASH PROGRAM READ
;
;
;MS Byte of Program Address to read
;
;LS Byte of Program Address to read
;
;Point to PROGRAM memory
;EE Read
;First instruction after BSF EECON1,RD executes normally
;Any instructions here are ignored as program
;memory is read in second cycle after BSF EECON1,RD
;
;W = LS Byte of Program Memory
;
;W = MS Byte of Program EEDATL
;
Preliminary
EEDATL and EEDATH registers will hold this value until
another read or until it is written to by the user.
Note 1: The two instructions following a program
2: Data EEPROM can be read regardless of
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
the setting of the CPD bit.
© 2009 Microchip Technology Inc.
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