PIC16F1826-I/MQ Microchip Technology, PIC16F1826-I/MQ Datasheet - Page 206

• Manufacturer Part Number: PIC16F1826-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1826-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 2kWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1826/27
23.2
The PIC16F/LF1827 allows each individual CCP mod-
ule to select the timer source that controls the CCP
module. Each module has an independent selection.
As the PIC16F/LF1826/27 has only one 16-bit timer
(Timer1), the Capture and Compare modes of the CCP
modules always uses Timer1.
The PIC16F/LF1827 has three 8-bit timers with
auto-reload (Timer2, Timer4 and Timer6), PWM mode
on the CCP modules can use any of these timers. The
PIC16F/LF1826 has one 8-bit timer (Timer2), which is
used in PWM mode.
REGISTER 23-2:
DS41391B-page 206
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-4
bit 3-2
bit 1-0
Note 1:
C4TSEL1
R/W-0/0
CCP Clock Selection
PIC16F/LF1827 only.
C4TSEL<1:0>: CCP4 Timer Selection bits
00 = CCP4 is based off Timer 2 in PWM Mode
01 = CCP4 is based off Timer 4 in PWM Mode
10 = CCP4 is based off Timer 6 in PWM Mode
11 = Reserved
C3TSEL<1:0>: CCP3 Timer Selection bits
00 = CCP3 is based off Timer 2 in PWM Mode
01 = CCP3 is based off Timer 4 in PWM Mode
10 = CCP3 is based off Timer 6 in PWM Mode
11 = Reserved
C2TSEL<1:0>: CCP2 Timer Selectionm bits
00 = CCP2 is based off Timer 2 in PWM Mode
01 = CCP2 is based off Timer 4 in PWM Mode
10 = CCP2 is based off Timer 6 in PWM Mode
11 = Reserved
C1TSEL<1:0>: CCP1 Timer Selection bits
00 = CCP1 is based off Timer 2 in PWM Mode
01 = CCP1 is based off Timer 4 in PWM Mode
10 = CCP1 is based off Timer 6 in PWM Mode
11 = Reserved
C4TSEL0
R/W-0/0
CCPTMRS: CCP TIMERS CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
C3TSEL1
R/W-0/0
C3TSEL0
R/W-0/0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
C2TSEL1
R/W-0/0
C2TSEL0
R/W-0/0
(1)
© 2009 Microchip Technology Inc.
C1TSEL1
R/W-0/0
C1TSEL0
R/W-0/0
bit 0