LP2996MR National Semiconductor, LP2996MR Datasheet - Page 15
![IC, REG DDR TERMINATION, SMD, PSOP8](/photos/19/7/190793/ge8psop05-40_sml.jpg)
LP2996MR
Manufacturer Part Number
LP2996MR
Description
IC, REG DDR TERMINATION, SMD, PSOP8
Manufacturer
National Semiconductor
Datasheet
1.LP2996M.pdf
(18 pages)
Specifications of LP2996MR
Primary Input Voltage
2.5V
Output Voltage
1.35V
No. Of Pins
8
Output Current
1.5A
Voltage Regulator Case Style
PSOP
Operating Temperature Range
0°C To +125°C
Svhc
No SVHC (15-Dec-2010)
Output Voltage Fixed
1.35V
Rohs Compliant
Yes
No. Of Outputs
1
Filter Terminals
SMD
Mounting Type
Surface Mount
Input Voltage Primary Max
5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCB Layout Considerations
1.
2.
3.
4.
The input capacitor for the power rail should be placed
as close as possible to the PVIN pin.
V
at the point where regulation is required. For
motherboard applications an ideal location would be at
the center of the termination bus.
V
either the DIMM or the Chipset. This provides the most
accurate point for creating the reference voltage.
For improved thermal performance excessive top side
copper should be used to dissipate heat from the
SENSE
DDQ
can be connected remotely to the V
should be connected to the V
TT
termination bus
DDQ
rail input at
15
5.
6.
package. Numerous vias from the ground connection to
the internal ground plane will help. Additionally these can
be located underneath the package if manufacturing
standards permit.
Care should be taken when routing the V
avoid noise pickup from switching I/O signals. A 0.1uF
ceramic capacitor located close to the
used to filter any unwanted high frequency signal. This
can be an issue especially if long
V
ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the
V
REF
REF
should be bypassed with a 0.01 µF or 0.1 µF
pin.
SENSE
SENSE
traces are used.
SENSE
www.national.com
can also be
trace to