LP2996MR National Semiconductor, LP2996MR Datasheet - Page 8

• Manufacturer Part Number: LP2996MR
• Description: IC, REG DDR TERMINATION, SMD, PSOP8
• Manufacturer: National Semiconductor

Specifications of LP2996MR

• Primary Input Voltage: 2.5V
• Output Voltage: 1.35V
• No. Of Pins: 8
• Output Current: 1.5A
• Voltage Regulator Case Style: PSOP
• Operating Temperature Range: 0°C To +125°C
• Svhc: No SVHC (15-Dec-2010)
• Output Voltage Fixed: 1.35V
• Rohs Compliant: Yes
• No. Of Outputs: 1
• Filter Terminals: SMD
• Mounting Type: Surface Mount
• Input Voltage Primary Max: 5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Description
The LP2996 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2. The output, V
capable of sinking and sourcing current while regulating the
output voltage equal to VDDQ / 2. The output stage has been
designed to maintain excellent load regulation while prevent-
ing shoot through. The LP2996 also incorporates two distinct
power rails that separates the analog circuitry from the power
output stage. This allows a split rail approach to be utilized to
decrease internal power dissipation. It also permits the
LP2996 to provide a termination solution for the next gener-
ation of DDR-SDRAM memory (DDRII). For new designs, the
LP2997 or LP2998 is recommended for DDR-II applications.
The LP2996 can also be used to provide a termination voltage
for other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termination.
This involves one R
memory and one R
R
scale the current requirements from the LP2996. This imple-
mentation can be seen below in
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2996. AVIN
is used to supply all the internal control circuitry. PVIN, how-
ever, is used exclusively to provide the rail voltage for the
output stage used to create VTT. These pins have the capa-
bility to work off separate supplies depending on the applica-
tion. Higher voltages on PVIN will increase the maximum
continuous output current because of output RDSON limita-
tions at voltages close to VTT. The disadvantage of high
values of PVIN is that the internal power loss will also in-
crease, thermally limiting the design. For SSTL-2 applica-
tions, a good compromise would be to connect the AVIN and
PVIN directly together at 2.5V. This eliminates the need for
bypassing the two supply pins separately. The only limitation
on input voltage selection is that PVIN must be equal to or
lower than AVIN. It is recommended to connect PVIN to volt-
age rails equal to or less than 3.3V to prevent the thermal limit
from tripping because of excessive internal power dissipation.
If the junction temperature exceeds the thermal shutdown
than the part will enter a shutdown state identical to the man-
ual shutdown where V
S
and R
T
FIGURE 1. SSTL-Termination Scheme
are 25 Ohms, although these can be changed to
T
S
termination resistor. Typical values for
TT
series resistor from the chipset to the
is tri-stated and V
Figure
1.
REF
remains active.
20057506
TT
is
8
VDDQ
VDDQ is the input used to create the internal reference volt-
age for regulating V
from a resistor divider of two internal 50kΩ resistors. This
guarantees that V
implementation of VDDQ is as a remote sense. This can be
achieved by connecting VDDQ directly to the 2.5V rail at the
DIMM instead of AVIN and PVIN. This ensures that the ref-
erence voltage tracks the DDR memory rails precisely without
a large voltage drop from the power lines. For SSTL-2 appli-
cations VDDQ will be a 2.5V signal, which will create a 1.25V
termination voltage at V
ble for exact values of V
V
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications the termi-
nation resistors will connect to V
voltage was regulated only at the output of the LP2996 then
the long trace will cause a significant IR drop resulting in a
termination voltage lower at one end of the bus than the other.
The V
connecting it to the middle of the bus. This will provide a better
distribution across the entire termination bus. If remote load
regulation is not used then the V
nected to V
is implemented in close proximity to the memory. Noise pick-
up in the V
regulation of V
to the V
and preventing errors.
SHUTDOWN
The LP2996 contains an active low shutdown pin that can be
used to tri-state VTT. During shutdown V
posed to voltages that exceed AVIN. With the shutdown pin
asserted low the quiescent current of the LP2996 will drop,
however, V
of 100kΩ for generating the internal reference. Therefore to
calculate the total power loss in shutdown both currents need
to be considered. For more information refer to the Thermal
Dissipation section. The shutdown pin also has an internal
pull-up current, therefore to turn the part on the shutdown pin
can either be connected to AVIN or left open.
V
V
voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory.
Since these inputs are typically an extremely high impedance,
there should be little current drawn from V
performance, an output bypass capacitor can be used, locat-
ed close to the pin, to help with noise. A ceramic capacitor in
the range of 0.1 µF to 0.01 µF is recommended. This output
remains active during the shutdown state and thermal shut-
down events for the suspend to RAM functionality.
V
V
resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2996 is
designed to handle peak transient currents of up to ± 3A with
a fast transient response. The maximum continuous current
is a function of V
FORMANCE CHARACTERISTICS section. If a transient is
expected to last above the maximum continuous current rat-
ing for a significant amount of time then the output capacitor
SENSE
REF
REF
TT
TT
is the regulated output that is used to terminate the bus
provides the buffered output of the internal reference
SENSE
SENSE
TT
DDQ
pin can be used to improve this performance, by
SENSE
. Care should be taken when a long V
TT
pin can help filter any high frequency signals
will always maintain its constant impedance
. A small 0.1uF ceramic capacitor placed next
IN
TT
trace can cause problems with precise
and can be viewed in the TYPICAL PER-
will track VDDQ / 2 precisely. The optimal
TT
. The reference voltage is generated
TT
TT
(See Electrical Characteristics Ta-
over temperature).
TT
SENSE
in a long plane. If the output
pin must still be con-
TT
REF
should not be ex-
. For improved
SENSE
trace