SE95DP NXP Semiconductors, SE95DP Datasheet - Page 12

• Manufacturer Part Number: SE95DP
• Description: IC, TEMP SENSOR, DIGITAL, 8TSSOP
• Manufacturer: NXP Semiconductors

Specifications of SE95DP

• Ic Output Type: Digital
• Sensing Accuracy Range: ± 2°C
• Supply Current: 150µA
• Supply Voltage Range: 2.8V To 5.5V
• Resolution (bits): 13bit
• Sensor Case Style: TSSOP
• No. Of Pins: 8
• Base Number: 95
• Temperature Sensing Range: -55°C To +125°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SE95_7
Product data sheet
8.7 Protocols for writing and reading the registers
The communication between the host and the SE95 must follow the rules strictly as
defined by the I
operations are illustrated in
10. A’: master acknowledge bit, not returned by the device, but set by the master or host
11. NA: not-acknowledge bit. During this clock period, both the device and host release
12. In a write protocol, data is sent from the host to the device and the host controls the
13. In a read protocol, data is sent to the bus by the device and the host must release the
1. Before a communication, the I
2. The host must provide SCL clock pulses necessary for the communication. Data is
3. During data transfer, except the START and STOP signals, the SDA signal must be
4. S: START signal, initiated by the host to start a communication, the SDA goes from
5. RS: RE-START signal, same as the START signal, to start a read command that
6. P: STOP signal, generated by the host to stop a communication, the SDA goes from
7. W: write bit, when the write/read bit is in a write command.
8. R: read bit, when the write/read bit is logic 1 in a read command.
9. A: device acknowledge bit, returned by the SE95. It is logic 0 if the device works
and SDA lines must both be released by all devices on the bus, and they become
HIGH by the bus pull-up resistors.
transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by
1-bit status of the acknowledgement.
stable while the SCL signal is HIGH. It means that the SDA signal can be changed
only during the LOW duration of the SCL line.
HIGH-to-LOW while the SCL is HIGH.
follows a write command.
LOW-to-HIGH while the SCL is HIGH. The bus becomes free thereafter.
properly and logic 1 if not. The host must release the SDA line during this period in
order to give the device the control on the SDA line.
in reading 2-byte data. During this clock period, the host must set the SDA line to
LOW in order to notify the device that the first byte has been read for the device to
provide the second byte onto the bus.
the SDA line at the end of a data transfer, the host is then enabled to generate the
stop signal.
SDA line, except during the clock period when the device sends the device
acknowledgement signal to the bus.
SDA line during the time that the device is providing data onto the bus and controlling
the SDA line, except during the clock period when the master sends the master
acknowledgement signal to the bus.
Ultra high accuracy digital temperature sensor and thermal watchdog
2
C-bus management. The protocols for SE95 register read/write
Rev. 07 — 2 September 2009
Figure 5
2
C-bus must be free or not busy. It means that the SCL
to
Figure 10
together with the following definitions:
© NXP B.V. 2009. All rights reserved.
SE95
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