PCA9691BS/1 NXP Semiconductors, PCA9691BS/1 Datasheet - Page 20

• Manufacturer Part Number: PCA9691BS/1
• Description: IC, ADC/DAC, 8-BIT, I2C, 16-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9691BS/1

• Brief Features: 8bit Successive Approximation A/D Conversion, Low Standby Current
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: VQFN
• No. Of: RoHS Compliant
• Ic Function: 8-bit A/D & D/A Converter
• Rohs Compliant: Yes

NXP Semiconductors
Table 7.
V
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
PCA9691_2
Product data sheet
Symbol Parameter
t
t
t
f
r
w(spike)
DD
DD
Fig 23. I
PROTOCOL
SDA
SCL
= 2.5 V to 5.5 V; V
(see
The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is
held LOW for a minimum of 25 ms. You must disable the bus time-out feature for DC operation.
t
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of the SCL’s falling edge.
C
The maximum t
series protection resistors to be connected between the SDA pin and the SDA bus line and between the SCL pin and the SCL bus line
without exceeding the maximum t
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
Figure
Rise and fall times refer to 30 % and 70 %
fall time of both SDA
and SCL signals
rise time of both
SDA and SCL
signals
spike pulse width
= minimum time for valid SDA (out) data following SCL LOW.
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
2
I
C-bus timing diagram
2
C-bus characteristics
23).
f
t
SU;STA
for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t
t
BUF
CONDITION
SS
START
(S)
t
= 0 V; T
HD;STA
Conditions
amb
f
t
.
LOW
…continued
t
=
r
BIT 7
MSB
−
(A7)
40
t
HIGH
°
C to +85
[4][5][6]
[4][5][6]
Rev. 02 — 27 January 2010
[7]
t
t
f
SU;DAT
°
1 / f
C; reference to 30 % and 70 % with an input voltage swing of V
Standard mode
Min
BIT 6
(A6)
SCL
-
-
-
t
HD;DAT
1000
Max
300
50
20 + 0.1C
20 + 0.1C
(R/W)
BIT 0
LSB
Min
Fast mode
-
t
VD;DAT
ACKNOWLEDGE
b
b
(A)
8-bit A/D and D/A converter
Max
300
300
50
IL
of the SCL signal) in order to
Fast-mode Plus Unit
f
Min
is 250 ns. This allows
PCA9691
-
-
-
© NXP B.V. 2010. All rights reserved.
CONDITION
STOP
(P)
t
SU;STO
Max
120
120
50
mbd820
20 of 31
SS
ns
ns
ns
to