ADE7762ARWZ Analog Devices Inc, ADE7762ARWZ Datasheet - Page 7

• Manufacturer Part Number: ADE7762ARWZ
• Description: IC, POLYPHASE ENERGY METERING, SOIC-28
• Manufacturer: Analog Devices Inc

Specifications of ADE7762ARWZ

• Ic Function: Polyphase Energy Metering IC With Phase Drop Indication
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Input Impedance: 140 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 8.5mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Brief Features: On-Chip Creep Protection, High Frequency Output
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADE7762EBZ - BOARD EVALUATION FOR ADE7762
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7, 8;
9, 10;
11, 12
13
14
15, 16, 17,
18
19
20
Mnemonic
LED_CTRL
LED_A
CF
DGND
V
REVP
IAP, IAN;
IBP, IBN;
ICP, ICN
AGND
REF
VN, VCP, VBP, VAP
ABS
SCF
DD
IN/OUT
Description
LED Control Output. The LED_CTRL signal multiplexes the indication of phase drop, phase sequence
error, and per phase reverse power on the LED_A, LED_B, and LED_C pins.
Phase A Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on Phase A (see the Phase Monitor section).
Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information.
This output is intended to be used for calibration purposes.
This provides the ground reference for the digital circuitry in the ADE7762, that is, multipliers, filters,
and digital-to-frequency converters. Because the digital return currents in the ADE7762 are small, it is
acceptable to connect this pin to the analog ground plane of the whole system.
Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7762. The supply
voltage should be maintained at 5 V ± 5% for a specified operation. This pin should be decoupled to
DGND with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor.
This logic output goes logic high when negative power is detected on the sum of the three phase
powers. This output is not latched and resets when positive power is once again detected (see the
Negative Total Power Detection section).
Analog Inputs for Current Channels. These channels are intended for use with current transducers and
are referenced in this document as current channels. These inputs are fully differential voltage inputs
with maximum differential input signal levels of ±0.5 V (see the Analog Inputs section). Both inputs
have internal ESD protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these
inputs without risk of permanent damage.
This pin provides the ground reference for the analog circuitry in the ADE7762 (ADCs and reference).
This pin should be tied to the analog ground plane or the quietest ground reference in the system. This
quiet ground reference should be used for all analog circuitry, such as antialiasing filters and current
and voltage transducers. To keep ground noise around the ADE7762 to a minimum, the quiet ground
plane should connect to the digital ground plane at only one point. It is acceptable to place the entire
device on the analog ground plane.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.4 V ± 8% and a typical temperature coefficient of 25 ppm/°C. An external reference source can also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic
capacitor.
Analog Inputs for the Voltage Channels. These channels are intended for use with voltage transducers
and are referenced in this document as voltage channels. These inputs are single-ended voltage inputs
with a maximum signal level of ±0.5 V with respect to VN for a specified operation. All inputs have
internal ESD protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.
This logic input is used to select the method by which the three active energies from each phase are
summed. It selects between the arithmetical sum of the three energies (ABS logic high) or the sum of
the absolute values (ABS logic low). See the Mode Selection of the Sum of the Three Active Energies
section.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table 7 shows how the calibration frequencies are selected.
LED_CTRL
REF
LED_A
DGND
AGND
IN/OUT 14
REVP
V
IAN
IBN
ICN
IAP
IBP
ICP
CF
DD
Figure 4. Pin Configuration
10
11
12
13
Rev. 0 | Page 7 of 28
1
2
3
4
5
6
7
8
9
(Not to Scale)
ADE7762
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LED_B
LED_C
F1
F2
S1
S0
CLKOUT
CLKIN
SCF
ABS
VAP
VBP
VCP
VN
ADE7762