ST62T08CB6 STMicroelectronics, ST62T08CB6 Datasheet - Page 26

• Manufacturer Part Number: ST62T08CB6
• Description: IC, 8BIT MCU OTP 1K, 62T08, DIP20
• Manufacturer: STMicroelectronics

Specifications of ST62T08CB6

• Controller Family/series: ST6
• Core Size: 8bit
• No. Of I/o's: 12
• Program Memory Size: 1KB
• Ram Memory Size: 64Byte
• Cpu Speed: 8MHz
• Oscillator Type: External Only
• No. Of Timers: 1
• Digital Ic Case: RoHS Compliant
• Peripherals: ADC, LVD
• Rohs Compliant: Yes
• Processor Series: ST62T0x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Data Ram Size: 64 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: Details

ST6208C/ST6209C/ST6210C/ST6220C
RESET (Cont’d)
5.3.4 Watchdog Reset
The MCU provides a Watchdog timer function in
order to be able to recover from software hang-
ups. If the Watchdog register is not refreshed be-
fore an end-of-count condition is reached, a
Watchdog reset is generated.
After a Watchdog reset, the MCU restarts in the
same way as if a Reset was generated by the RE-
SET pin.
Note: When a watchdog reset occurs, the RESET
pin is tied low for very short time period, to flag the
reset phase. This time is not long enough to reset
external circuits.
For more details refer to the Watchdog Timer
chapter.
5.3.5 LVD Reset
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
During an LVD reset, the RESET pin is pulled low
when V
edge).
For more details, refer to the LVD chapter.
Caution: Do not externally connect directly the
RESET pin to V
component in case of internal RESET (Watchdog
or LVD).
Figure 15. Simple External Reset Circuitry
26/104
1
Typical: R = 10K
Power-On RESET
Voltage Drop RESET
V
DD
DD
C = 10nF
<V
IT+
DD
(rising edge) or V
R
C
, this may cause damage to the
V
RESET
DD
R > 4.7 K
ST62xx
DD
<V
IT-
(falling
Figure 16. Reset Processing
YES
FROM RESET LOCATIONS
FETCH INSTRUCTION
INT LATCH CLEARED
ON ADDRESS BUS
NMI MODE FLAGS
IS RESET STILL
NMI MASK SET
(IF PRESENT)
PUT FFEh
FFEh/FFFh
INTERNAL
PRESENT?
LOAD PC
SELECT
RESET
RESET
CLOCK CYCLE
NO
DELAY
2048