CDB4350 Cirrus Logic Inc, CDB4350 Datasheet - Page 18

• Manufacturer Part Number: CDB4350
• Description: Eval Bd 105dB 192kHz DAC W/PLL
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4350

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4350
• Description/function: Audio D/A
• Operating Supply Voltage: 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4350
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1517

18
4. APPLICATIONS
4.1
4.1.1
4.2
4.2.1
Sample Rate Range and Oversampling Mode Detect
The device operates in one of three oversampling modes based on the input sample rate. In Control Port
Mode, the allowed sample rate range in each mode will depend on how the FM[1:0] bits are configured. In
Stand-Alone Mode, the sample rate range will be according to
System Clocking
The device requires external generation of the left/right (LRCK) and serial (SCLK) clocks. The left/right clock
frequency is equal to the input sample rate (Fs).
Refer to
mat, and
quencies.
Sample Rate Auto-Detect
The Auto-Detect feature is enabled by default. In this state, the CS4350 will auto-detect the correct mode
when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges shown in
Table
enabled.
In Control Port Mode, the Auto-Detect feature can be disabled by the Functional Mode (FM[1:0]) bits in
the control port register 02h. In this state, the CS4350 will not auto-detect the correct mode based on the
input sample rate (Fs). The operational mode must then be set manually according to one of the ranges
referred to in
In Stand-Alone Mode it is not possible to disable auto-detect of sample rates.
Recovered Master Clock (RMCK)
The CS4350 generates a high-frequency master clock (RMCK) which it derives from the LRCK input,
available on the RMCK pin. In Stand-Alone Mode, the frequency of RMCK is equal to 256 x LRCK in Sin-
gle-Speed and Double-Speed Mode; and 128 x LRCK in Quad-Speed Mode. In Control-Port Mode, the
frequency of the RMCK signal can be selected through register 08h (see
details).
1. Sample rates outside the specified range for each mode are not supported when Auto-Detect is
Section 4.3
“Switching Specifications - Serial Audio Interface” on page 13
Section
Input Sample Rate (Fs)
120 kHz - 216 kHz
for the required SCLK-to-LRCK timing associated with the selected digital interface for-
60 kHz - 108 kHz
30 kHz - 54 kHz
8.2.3. Sample rates outside the specified range for each mode are not supported.
Table 1. CS4350 Auto-Detect
Table
1.
Double-Speed Mode
Single-Speed Mode
for the maximum allowed clock fre-
Quad-Speed Mode
Section 8.7 on page 34
Mode
CS4350
DS691F1
for more