CDB4350 Cirrus Logic Inc, CDB4350 Datasheet - Page 25

• Manufacturer Part Number: CDB4350
• Description: Eval Bd 105dB 192kHz DAC W/PLL
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4350

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4350
• Description/function: Audio D/A
• Operating Supply Voltage: 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4350
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1517

DS691F1
6. CONTROL PORT OPERATION
The control port is used to load all the internal register settings (see
ation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential
interference problems, the control port pins should remain static if no operation is required.
The control port can operate in I²C or SPI mode.
6.1
6.2
6.2.1
6.2.2
MAP Auto Increment
The device has a MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for consecutive writes or reads. If INCR is
set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of con-
secutive registers.
I²C Mode
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see
enable the user to alter the chip address (10010[AD1][AD0][R/W]) and should be tied to VLC or GND as
required before powering up the device. SPI Mode will be selected if the device ever detects a high to low
transition on the AD0/CS pin after power-up.
I²C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by
4. If the INCR bit (see
5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate
I²C Read
To read from the device, follow the procedure below while adhering to the control port switching specifi-
cations in
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
10010. The sixth and seventh bit must match the settings of the AD1 and AD0 pins respectively, and
the eighth must be 0 (the eighth bit of the address byte is the R/W bit).
byte points to the register to be written.
the MAP.
written, then initiate a STOP condition to the bus.
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
10010. The sixth and seventh bits must match the setting of the AD1 and AD0 pins, respectively, and
the eighth must be 1. The eighth bit of the address byte is the R/W bit.
pointed to by the MAP. The MAP register will contain the address of the last register written to the
”Switching Characteristics - Control Port - I²C Format” on page
”Switching Characteristics - Control Port - I²C Format” on page
Section
Figure 19
6.1) is set to 1, repeat the previous step until all the desired registers are
for the clock to data relationship). There is no CS pin. AD1 and AD0
”Register Description” on page
14.
14.
29). The oper-
CS4350
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