CS4340-KS Cirrus Logic Inc, CS4340-KS Datasheet - Page 20

• Manufacturer Part Number: CS4340-KS
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4340-KS

• Resolution (bits): 24bit
• Data Interface: Serial
• No. Of Pins: 16
• Update Rate: 96kSPS
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• No. Of Bits: 24 Bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.7
The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The
pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and
right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This
pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in
any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in
extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340 data sheet
for a suggested mute circuit.
4.8
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrange-
ments if its potential performance is to be realized. Figure 14 shows the recommended power arrangements, with
VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND
& AGND should be connected to the analog ground plane.
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the
closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling
into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to mini-
mize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on
the same layer as the DAC. The CDB4340 evaluation board demonstrates the optimum layout and power supply
arrangements.
20
Mute Control
Grounding and Power Supply Arrangements
CS4340
DS297F3