CS47048C-DQZ Cirrus Logic Inc, CS47048C-DQZ Datasheet - Page 25

• Manufacturer Part Number: CS47048C-DQZ
• Description: IC 4ch ADC 8ch DAC & Single Core 32-bit DSP Audio SoC (300M MACs)
• Manufacturer: Cirrus Logic Inc

Specifications of CS47048C-DQZ

• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 100
• Peak Reflow Compatible (260 C): Yes
• Frequency: 147MHz
• Embedded Interface Type: I2C, SPI
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Core Supply Voltage: 1.89V
• Digital Ic Case Style: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.14 Digital Switching Characteristics — Digital Audio Output Port
DS787PP5
DAO_MCLK period
DAO_MCLK duty cycle
DAO_SCLK period for Master or Slave mode
DAO_SCLK duty cycle for Master or Slave mode
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
DAO_LRCLK to DAO_SCLK non-active edge
DAO_SCLK non-active edge
DAO_DATA[3:0] delay from DAO_SCLK non-active edge
DAO_LRCLK to DAO_SCLK non-active edge
13A.
DAO_SCLK non-active edge
13B.
DAO1_DATA[3.0] delay from DAO_SCLK non-active edge
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAO_DATAn
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it
3. The DAO_LRCLK transition may occur on either side of the non-active edge of DAO_LRCLK. The active edge
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
5. These Max values for t
is divided to produce DAO_SCLK, DAO_LRCLK.
of DAO_SCLK is the point at which the data is valid.
of the maximum delays.
A. DAO_LRCLK transition before DAO_SCLK non-active
edge. See
Master Mode (Output A1 Mode)
Slave Mode (Output A0 Mode)
Footnote 3 on page 25.
Figure 12.
Parameter
daoslrts
3
t
3, 5
daomclk
to DAO_LRCLK, See
t
to DAO_LRCLK, See
daomsck
and t
Digital Audio Output Port Timing, Master Mode
daosstlr
Copyright 2011 Cirrus Logic
t
1
3
daomlrts
3,5
. See
apply to applications where a 1/2 period of DAO_SCLK exceeds one
t
daomdv
1,2
4
See
1
Figure 12A.
Figure 12B.
Figure
Figure
3
3
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAO_DATAn
B. DAO_LRCLK transition after DAO_SCLK non-active
edge. See
Symbol
T
t
t
T
t
t
t
t
daomsck
t
daomlrts
daomstlr
daomdv
daoslrts
daosstlr
daomclk
daosdv
daosclk
-
-
Footnote 3 on page 25.
Min
20
45
20
40
t
t
daomdv
-
-
-
-
-
-
-
daomstlr
Audio SOC Processor Family
t
daomclk
t
daomsck
CS470xx Data Sheet
Max
55
60
19
15
30
8
8
8
8
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
25