CS5102A-BL Cirrus Logic Inc, CS5102A-BL Datasheet - Page 20

• Manufacturer Part Number: CS5102A-BL
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-BL

• Input Channels Per Adc: 2
• Mounting Type: Surface Mount
• No. Of Channels: 2
• Power Rating: 44mW
• Supply Voltage Min: 4.5V
• Peak Reflow Compatible (260 C): No
• Sample Rate: 20kSPS
• Supply Voltage Max: 5.5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.6.2
RBT mode is selected by tying SCKMOD high, and
OUTMOD low. As in PDT mode, SCLK is an input,
however data is available immediately following
conversion, and may be clocked out the moment
TRK1 or TRK2 falls. The falling edge of
clears the output buffer, so any unread data will be
lost. A new conversion may be initiated before all
the data has been clocked out if the unread data
bits are not important (Figure 6).
4.6.3
SSC mode is selected by tying SCKMOD low, and
OUTMOD high. In SSC mode, SCLK is an output,
and will clock out each bit of the data as it's being
converted. SCLK will remain high between conver-
sions, and run at a rate of 1/4 the master clock
speed for 16 low pulses during conversion
(Figure 7).
The SSH/SDL goes low coincident with the first
falling edge of SCLK, and returns high 2 CLKIN cy-
cles after the last rising edge of SCLK. This signal
frames the 16 data bits and is useful for interfacing
20
Register Burst Transmission (RBT)
Synchronous Self-clocking (SSC)
C LK IN (i)
H O LD (i)
C H 1/2 (i)
In tern al
S tatus
S C LK (i)
S D A TA (o )
S S H /S D L (o )
T R K1 (o )
T R K2 (o )
0
D 15
4
C onverting C h. 2
D 14
Figure 5. Pipelined Data Transmission (PDT) Mode Timing
8
D 1 D 0 (C h. 1)
60
64
68
T racking C h. 1
HOLD
72
76
0
to shift registers (e.g. 74HC595) or to DSP serial
ports.
4.6.4
Free Run is the internal, synchronous loopback
mode. FRN mode is selected by tying SCKMOD
and OUTMOD low. SCLK is an output, and oper-
ates exactly the same as in the SSC mode. In Free
Run mode, the converter initiates a new conver-
sion every 80 master clock cycles, and alternates
between channel 1 and channel 2. HOLD is dis-
abled, and should be tied to either VD+ or DGND.
CH1/
each new conversion cycle, indicating which chan-
nel will be tracked after the current conversion is
finished (Figure 8).
The SSH/SDL goes low coincident with the first
falling edge of SCLK, and returns high 2 CLKIN cy-
cles after the last rising edge of SCLK. This signal
frames the 16 data bits and is useful for interfacing
to shift registers (e.g. 74HC595) or to DSP serial
ports.
D 15
4
2
C onverting C h. 1
D 14
is an output, and will change at the start of
8
Free Run (FRN)
D 1
60
D 0 (C h. 2)
6 4
CS5101A CS5102A
68
T racking C h. 2
72
76
0
D 15
DS45F6