CS5460A-BS Cirrus Logic Inc, CS5460A-BS Datasheet - Page 22

• Manufacturer Part Number: CS5460A-BS
• Description: Driver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5460A-BS

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Driver Case Style: SSOP
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EXAMPLE #2: The required number of pulses per
unit energy present at EOUT is specified to be
500 pulses/kW-hr;
line-voltage is 250 V (RMS) and the maximum
line-current is 20 A (RMS). In such a situation, the
nominal line voltage and current do not determine
the appropriate pulse-rate setting. Instead, the
maximum line levels must be considered. As be-
fore, the given maximum line-voltage and line-cur-
rent levels are used to determine K
Again the sensor gains are calculated such that the
maximum line-voltage and line-current levels will
measure as 0.6 in the RMS Voltage Register and
RMS Current Register.
The required Pulse-Rate Register setting is now
determined by using the following equation:
Therefore PR = ~1.929 Hz.
Note that the Pulse-Rate Register cannot be set to
a frequency of exactly 1.929 Hz. The closest set-
ting that the Pulse-Rate Register can obtain is
0x00003E = 1.9375 Hz. To improve the accuracy,
either gain register can be programmed to correct
for the round-off error in PR. This value would be
calculated as
In the last example, suppose a value for MCLK/K
of 3.05856 MHz. When MCLK/K is not equal to
4.096 MHz, the result for ‘PR’ that is calculated for
the Pulse-Rate Register must be scaled by a cor-
rection factor of: 4.096 MHz / (MCLK/K). In this
case the result is scaled by 4.096/3.05856 to get a
final PR result of ~2.583 Hz.
3.2 Pulse Output for Normal Format,
Stepper Motor Format and Mechanical
Counter Format
The duration and shape of the pulse outputs at the
EOUT and EDIR pins can be set for three different
output formats. The default setting is for Normal
output pulse format. When the pulse is set to either
22
K
K
PR
Ign or Vgn
V
I
= 150 mV / 20 A = 0.0075 Ω
= 150 mV / 250 V = 0.0006
=
500
------------------
kW hr
pulses
=
⋅
------------ -
1.929
PR
⋅
------------- -
3600s
≅
1hr
given
1.00441
⋅
----------------- -
1000W
1kW
that
=
0x404830
⋅
250mV
----------------- -
K
the
V
V
and K
⋅
250mV
----------------- -
maximum
K
I
I
:
of the other two formats, the time duration and/or
the relative timing of the EOUT and EDIR pulses is
increased/varied such that the pulses can drive ei-
ther an electro-mechanical counter or a stepper
motor. The EOUT and EDIR output pins are capa-
ble of driving certain low-voltage/low-power
counters/stepper motors directly. This depends on
the drive current and voltage level requirements of
the counter/motor. The ability to set the pulse out-
put format to one of the three available formats is
controlled by setting certain bits in the Control Reg-
ister.
3.2.1 Normal Format
Referring to the description of the Control Register
in Section 5., Register Descriptions, if both the
MECH and STEP bits are set to ‘0’, the pulse out-
put format at the EOUT and EDIR pins is illustrated
in Figure 10. These are active-low pulses with very
short duration. The pulse duration is an integer
multiple of MCLK cycles, approximately equal to
1/16 of the period of the contents of the Pulse-Rate
Register. However for Pulse-Rate Register set-
tings less than the sampling rate (which is
[MCLK/8]/1024), the pulse duration will remain at a
constant duration, which is equal to the duration of
the pulses when the Pulse-Rate Register is set to
[MCLK/K]/1024. The maximum pulse frequency
from the EOUT pin is therefore [MCLK/K]/16.
When energy is positive, EDIR is always high.
When energy is negative, EDIR has the same out-
put as EOUT. When MCLK/K is not equal to
4.096 MHz, the true pulse-rate can be found by
first calculating what the pulse-rate would be if a
4.096 MHz crystal is used (with K = 1) and then
scaling
(MCLK/K) / 4.096 MHz.
When set to run in Normal pulse output format, the
pulses may be sent out in “bursts” depending on
both the value of the Pulse-Rate Register as well
as the amount of billable energy that was regis-
tered by the CS5460A over the most recent A/D
sampling period, which is (in Hz): 1 / [(MCLK/K) /
1024]. A running total of the energy accumulation
is maintained in an internal register (not accessible
to the user) inside the CS5460A. If the amount of
energy that has accumulated in this register over
the most recent A/D sampling period is equal to or
greater than the amount of energy that is repre-
the
result
by
a
CS5460A
factor
DS487F4
of