CS8415A-CSZ Cirrus Logic Inc, CS8415A-CSZ Datasheet - Page 13

• Manufacturer Part Number: CS8415A-CSZ
• Description: IC,Digital Audio Receiver,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CSZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS8415A
4. SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The port can be adjusted to suit the attached device setting the control
registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolution,
left or right justification of the data relative to left/right clock, optional one-bit cell delay of the first data bit, the polar-
ity of the bit clock, and the polarity of the left/right clock. By setting the appropriate control bits, many formats are
possible.
Figure 6
shows the selection of common output formats including the control bit settings. It should be noted that in
right-justified mode, the serial audio output data is "MSB extended". This means that in a sub-frame where the
MSB of the data is '1', all bits preceding the MSB in the sub-frame will also be '1'. Conversely, in a sub-frame where
the MSB of the data is '0', all bits preceding the MSB in the sub-frame will also be '0'.
A special AES3 direct output format is included, which allows the serial output port access to the V, U, and C bits
embedded in the serial audio data stream. The P bit is replaced by a Z bit that marks the subframe just prior to the
start of each block. The received channel status block start signal is only available in hardware mode, as the RCBL
pin.
In master mode, the left/right clock and the serial bit clock are outputs, derived from the recovered RMCK clock. In
slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the
appropriate master clock, but the serial bit clock can be asynchronous and discontinuous if required. By appropri-
ate phasing of the left/right clock and control of the serial clocks, multiple CS8415As can share one serial port. The
left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if
enough serial clocks are present in each phase to clock all the data bits. When in slave mode, the serial audio out-
put port must not be set for right-justified data. When using the serial audio output port in slave mode with an
OLRCK input which is asynchronous to the incoming AES3 data, an interrupt bit (OSLIP) is provided to indicate
DS470F4
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