CS8415A-CSZ Cirrus Logic Inc, CS8415A-CSZ Datasheet - Page 38

• Manufacturer Part Number: CS8415A-CSZ
• Description: IC,Digital Audio Receiver,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CSZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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14.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER
14.1
14.2
MANAGEMENT
AES3 Channel Status (C) Bit Management
The CS8415A contains sufficient RAM to store a full block of C data for both A and B channels (192 x 2 =
384 bits), and also 384 bits of U information. The user may read from these buffer RAMs through the control
port.
The buffering scheme involves 2 block-sized buffers, named D and E, as shown in
each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at
control port address 20h) is the consumer/professional bit for channel status block A.
The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks
of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the C data.
Accessing the E Buffer
The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of
the CS8415A, through the control port.
The user can configure the interrupt enable register to cause interrupts to occur whenever D-to-E buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is a D-to-E inhibit bit. This may be used whenever “long” control port interactions are occur-
ring.
From
AES3
Receiver
Figure 16. Channel Status Data Buffer Structure
Received
Data
Buffer
D
8-bits
A
Control Port
words
E
8-bits
24
B
Figure
16. The MSB of
CS8415A
DS470F4