CS8415A-CSZ Cirrus Logic Inc, CS8415A-CSZ Datasheet - Page 19

• Manufacturer Part Number: CS8415A-CSZ
• Description: IC,Digital Audio Receiver,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CSZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS470F4
6.2
6.3
Notes:
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with
the clock to data relationship as shown in
a unique address. Pins AD0 and AD1 form the two least significant bits of the chip address and should be
connected to VL+ or DGND as desired. The EMPH pin is used to set the AD2 bit by connecting a resistor
from the EMPH pin to VL+ or to DGND. The state of the pin is sensed while the CS8415A is being reset.
The upper 4 bits of the 7-bit address field are fixed at 0010b. To communicate with a CS8415A, the chip
address field, which is the first byte sent to the CS8415A, should match 0010b followed by the settings of
the EMPH, AD1, and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next
byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation
is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in
MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the CS8415A after each input byte is read, and is input to the CS8415A from
the microcontroller after each transmitted byte. I²C mode is supported only with VL+ in 5V mode.
Interrupts
The CS8415A has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be set to be active-low, active-high or active-low with
no active pull-up transistor. This last mode is used for active-low, wired-OR hook-ups, with multiple periph-
erals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source
may be masked off through mask register bits. In addition, each source may be set to rising edge, falling
edge, or level-sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er.
1. AD2 is derived from a resistor attached to the EMPH pin.
2. If operation is a write, this byte contains the Memory Address Pointer, MAP.
3. If operation is a read, the last bit of the read should be NACK (high).
AD1 and AD0 are determined by the state of the corresponding pins.
SDA
SCL
Start
0010
Figure 9. Control Port Timing in I²C Mode
AD2-0
Note 1
R/W
Figure
ACK DATA7-0 ACK DATA7-0 ACK
9. There is no CS pin. Each individual CS8415A is given
Note 2
Note 3
Stop
CS8415A
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