DS92CK16TMTC National Semiconductor, DS92CK16TMTC Datasheet - Page 5

• Manufacturer Part Number: DS92CK16TMTC
• Description: IC,Six Distributed-Output Clock Driver,CMOS,TSSOP,24PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of DS92CK16TMTC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
t
t
t
t
t
t
t
t
t
t
t
f
PHLDD
PLHDD
PHLCrd
PLHCrd
SK1D
SK2D
TLHD
THLD
PHZD
PLZD
PZHD
PZLD
MAX
Symbol
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 7, 8).
Switching Characteristics
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the
devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: ESD Rating: ESD qualification is performed per the following: HBM (1.5 k , 100 pF), Machine Model (250V, 0 ), IEC 1000-4-2. All VCC pins connected to-
gether, all ground pins connected together.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD, VTH,
and VTL.
Note 4: All typicals are given for: V
Note 5: The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |V
and CLKI/O− inputs, with the Common Mode set to V
Note 6: Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
Note 7: C
Note 8: Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50 , t
minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V. In general, the faster the input edge rate, the better
the AC performance.
Note 9: All device output transition times are based on characterization measurements and are guaranteed by design.
Note 10: t
V
Note 11: t
is guaranteed by design and characterization.
Note 12: t
applies to devices over recommended operating temperature and voltage ranges, and across process distribution. T
gation delay.This parameter is guaranteed by design and characterization.
Note 13: t
Note 14: t
plies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
delay.
Note 15: Generator input conditions: t
2.7V, Load = 7 pF (stray plus probes).
CC
. The propagation delay specification is a device to device worst case over process, voltage and temperature.
L
SK2R
SK1R
SK3R,
SK1D
SK2D
includes probe and fixture capacitance.
Differential Propagation Delay High to Low. CrdCLK
to CLKI/O
Differential Propagation Delay Low to High. CrdCLK
to CLKI/O
CrdCLK
CrdCLK
Duty Cycle Distortion (pulse skew)
|t
Differential Part-to-Part Skew (Note 14)
Differential Transition Time (Note 9)
(20% to 80% )
Differential Transition Time (Note 9)
(80% to 20% )
Transition Time High to TRI-STATE. DE to CLKI/O
Transition Time Low to TRI-STATE. DE to CLKI/O
Transition Time TRI-STATE to High. DE to CLKI/O
Transition Time TRI-STATE to Low. DE to CLKI/O
Maximum Operating Frequency (Note 15)
PLH
is the difference in receiver propagation delay (|t
is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter
part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This specification ap-
is the difference in driver propagation delay (|t
part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. This specification
–t
PHL
IN
IN
| (Note 13)
to CLK
to CLK
CC
OUT
OUT
r
/t
= +3.3V and T
f
<
Propagation Delay High to Low
Propagation Delay Low to High
Parameter
1 ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, V
A
CC
= +25˚C.
/2.
(Continued)
PLH
PLH
–t
–t
PHL
PHL
|) and is the duty cycle distortion of the CLKI/O outputs.
|) of one device, and is the duty cycle distortion of the output at any given temperature and
5
IN
IN
C
R
Figures 6, 7
C
Figures 8, 9
V
C
R
Figures 10, 11
IN
L
L
L
L
L
r
= 1 ns, t
= 15 pF
= 37.5
= 15 pF
= 15 pF,
= 37.5
= 0V to V
Conditions
f
= 1 ns (10%–90%). To ensure fastest propagation delay and
CC
SK2D
SK3R
is defined as Max–Min differential propagation
CC
–0V| may be applied between the CLKI/O+
Min
100
0.5
0.5
2.0
2.0
0.4
0.4
is defined as Max–Min differential propa-
0.75
0.75
Typ
125
1.8
1.8
4.5
4.5
OL
(max) 0.4V, V
Max
600
2.5
2.5
6.0
6.0
2.0
1.4
1.4
10
10
32
32
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Units
(min)
MHz
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns