DSPIC30F5011-20E/PT Microchip Technology, DSPIC30F5011-20E/PT Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F5011-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5011-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5011-20E/PTG; DSPIC30F501120EPT; DSPIC30F501120EPT

dsPIC30F5011/5013
TABLE 2:
DS80453E-page 2
Note 1:
Operations
Controller
Compare
Compare
Interrupt
Module
Output
Output
UART
I
CPU
CPU
CPU
CPU
ADC
PSV
2
DCI
PLL
PLL
I
C™
2
C
Only those issues indicated in the last column apply to the current silicon revision.
on U1MODE
Modification
PWM Mode
Sleep Mode
Instructions
on I2CCON
on I2CTRN
Operations
Operations
Operations
MAC Class
Instruction
Nested DO
Instruction
Idle Mode
U2MODE
4x Mode
8x Mode
Feature
Address
SILICON ISSUE SUMMARY
with ±4
DAW.b
Loops
Read
SFRs
DISI
Write
Write
SFR
SFR
and
—
—
—
Number
Item
10.
11.
12.
13.
14.
15.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly clear
the Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>)
will produce unexpected results.
Read operations performed on the I2CCON Special Function
Register (SFR) may yield incorrect results at operation over 20
MIPS.
Write operations performed on the I2CTRN SFR may yield
incorrect results at operation over 20 MIPS.
Write operations performed on the U1MODE and U2MODE
SFRs may yield incorrect results at operation over 20 MIPS.
The DCI module should not be stopped when the device
enters Idle mode.
The 4x PLL mode of operation may not function correctly for
certain input frequencies.
An interrupt occurring immediately after modifying the CPU
IPL, interrupt IPL, interrupt enable or interrupt flag may cause
an address error trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after
the glitch.
The Output Compare module will produce a glitch on the
output when an I/O pin is initially set high and the module is
configured to drive the pin low at a specified time.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPI bits are non-zero.
If 8x PLL mode is used, the input frequency range is 5 MHz-
10 MHz instead of 4 MHz-10 MHz.
Issue Summary
© 2010 Microchip Technology Inc.
A1 A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X