KS8721B Micrel Inc, KS8721B Datasheet
KS8721B
Specifications of KS8721B
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KS8721B Summary of contents
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... The KS8721B/BT can automatically configure itself for 100 or 10 Mbps and full or half duplex operation, using on-chip Auto- Negotiation algorithm ideal choice of physical layer transceiver for 100BaseTX/10BaseT applications ...
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... M9999-041405 Ordering Information Part Number Temperature Range KS8721B 0°C to +70°C KS8721BI –40°C to +85°C KSZ8721B 0°C to +70°C KS8721BT 0°C to +70°C KSZ8721BT 0°C to +70°C 2 Micrel, Inc. Package 48-Pin SSOP 48-Pin SSOP 48-Pin SSOP Lead Free 48-Pin TQFP ...
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... Add normal operating condition table & Thermal data for SSOP48 table Add Reset Timing table & Transformer Lists Add 48 TQFP pinout diagram & RMII AC Charateristics Add ordering info for 48 Pin TQFP package, KS8721B/BTI industrial temperature, KSY8721B/KSY8721BT environmentally friendly part number 2.2 8/29/03 Change part number from KS8721B to KS8721B/BT ...
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... KS8721B/BT Table Of Contents Pin Description ............................................................................................................................................................ 6 Strapping Option ......................................................................................................................................................... 9 Pin Configuration ...................................................................................................................................................... 10 Introduction ........................................................................................................................................................... 11 100BaseTX Transmit ........................................................................................................................................... 11 100BaseTX Receive ............................................................................................................................................ 11 PLL Clock Synthesizer ......................................................................................................................................... 11 Scrambler/De-scrambler (100BaseTX only) ........................................................................................................ 11 10BaseT Transmit ............................................................................................................................................... 11 10BaseT Receive ................................................................................................................................................ 11 SQE and Jabber Function (10Base only) ............................................................................................................ 11 Auto-Negotiation .................................................................................................................................................. 11 MII Management Interface ................................................................................................................................... 12 MII Data Interface ................................................................................................................................................ 12 Transmit Clock ............................................................................................................................................. 12 Receive Clock .............................................................................................................................................. 12 Transmit Enable ...
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... KS8721B/BT Absolute Maximum Ratings ..................................................................................................................................... 22 Operating Ratings ..................................................................................................................................................... 22 Electrical Characteristics .......................................................................................................................................... 22 Timing Diagrams ....................................................................................................................................................... 24 Selection of Isolation Transformers ........................................................................................................................ 30 Selection of Reference Crystals ............................................................................................................................... 30 Package Outline and Dimensions ............................................................................................................................ 31 April 2005 5 Micrel, Inc. M9999-041405 ...
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... KS8721B/BT Pin Description Pin Number Pin Name Type 1 MDIO 2 MDC 3 RXD3/ Ipd/O PHYAD1 4 RXD2/ Ipd/O PHYAD2 5 RXD1/ Ipd/O PHYAD3 6 RXD0/ Ipd/O PHYAD4 7 VDDIO 8 GND GND 9 RXDV/ Ipd/O CRSDV/ PCS_LPBK 10 RXC 11 RXER/ISO Ipd/O 12 GND GND 13 VDDC 14 TXER 15 TXC/ Ipu/O REFCLK 16 TXEN 17 TXD0 ...
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... KS8721B/BT Pin Number Pin Name Type 25 INT#/ Ipu/O PHYAD0 22 CRS/ Ipd/O RMII_BTB 23 GND GND 26 LED0/TEST Ipu/O 27 LED1/ Ipu/O SPD100/ noFEF 28 LED2/ Ipu/O DUPLEX 29 LED3/ Ipu/O NWAYEN 30 PD# 31 VDDRX 32 RX- 33 RX+ 34 FXSD/FXEN Ipd/O 35 GND GND 36 GND GND Note 1. Pwr = power supply GND = ground ...
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... KS8721B/BT Pin Number Pin Name Type 37 REXT 38 VDDRCV 39 GND GND 40 TX- 41 TX+ 42 VDDTX 43 GND GND 44 GND GND VDDPLL 48 RST# Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise ...
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... KS8721B/BT (Note 1) Strapping Options Pin Number Pin Name Type 6,5, PHYAD[4:1]/ Ipd/O 4,3 RXD[0:3] 25 PHYAD0/ Ipu/O INT# (3) 9 PCS_LPBK/ Ipd/O RXDV (3) 11 ISO/RXER Ipd/O (3) 21 RMII/COL Ipd/O (3) 22 RMII_BTB Ipd/O CRS 27 SPD100/ Ipu/O No FEF/ LED1 28 DUPLEX/ Ipu/O LED2 29 NWAYEN/ Ipu/O LED3 ...
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... KS8721B/BT Pin Configuration MDIO 1 MDC 2 R3D3/PHYAD1 3 RXD2/PHYAD2 4 RXD1/PHYAD3 5 RXD0/PHYAD4 6 VDDIO 7 GND 8 RXDV/PCS_LPBK 9 RXC 10 RXER/ISO 11 GND 12 VDDC 13 TXER 14 TXC/REF_CLK 15 TXEN 16 TXD0 17 TXD1 18 TXD2 19 TXD3 20 COL/RMII 21 CRS/RMII_BTB 22 GND 23 VDDIO 24 48-Pin SSOP (SM) M9999-041405 48 RST# 47 VDDPLL GND 43 GND 42 VDDTX 41 TX+ 40 TX- 39 GND 38 VDDRCV 37 REXT MDIO ...
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... RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8721B/BT decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception. ...
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... When the KS8721B/BT receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8721B/BT detects the second code words, it then configures itself according to above-mentioned priority. In addition, the KS8721B/BT also checks 100BaseTX idle or 10BaseT NLP symbol ...
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... KS8721B/BT Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721B/ BT asserts its collision signal, which is asynchronous to any clock. RMII (Reduced MII) Data Interface RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch or Repeater ASICs ...
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... KS8721B/BT Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] shall be “00” to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than “00” when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than “00” on TXD[1:0] while TX_EN is deasserted shall be ignored by the PHY ...
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... KS8721B/BT RMII Receive Timing REF_CLK RXD[1:0] RXDV RXER Parameter REF_CLK Frequency RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge Auto Crossover (Auto MDI/MDI-X) Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below. ...
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... MAC. FEF can be disabled by strapping pin 27 low. Refer to “Strapping Options” section. Media Converter Operation KS8721B/BT is capable of performing media conversion with 2 parts in a back to back RMII loop-back mode as indicated in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pin 21 and 22 strapped high). One part is operating at TX mode and the other in FX mode ...
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... KS8721B/BT Register Map Register No. Description 0h Basic Control Register 1h Basic Status Register 2h PHY Identifier I 3h PHY Identifier II 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register 6h Auto-Negotiation Expansion Register 7h Auto-Negotiation Next Page Register 8h Link Partner Next Page Ability 15h RXER Counter Register ...
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... KS8721B/BT Address Name 1.10:7 Reserved 1.6 No Preamble 1.5 Auto-Negotiation Complete 1.4 Remote Fault 1.3 Auto-Negotiation Ability 1.2 Link Status 1.1 Jabber Detect 1.0 Extended Capability Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Register 3h - PHY Identifier 2 3.15:10 PHY ID Number 3.9:4 Model Number 3.3:0 ...
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... KS8721B/BT Address Name 5.11:10 Pause 5.9 100 BaseT4 5.8 100BaseTX Full Duplex 5.7 100BaseTX 5.6 10BaseT Full Duplex 5.5 10BaseT 5.4:0 Selector Field Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved 6.4 Parallel Detection Fault 6.3 Link Partner Next Page Able 6.2 Next Page Able 6 ...
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... KS8721B/BT Address Name Register 15h - RXER Counter 15.15:0 RXER Counter Register 1bh - Interrupt Control/Status Register 1b.15 Jabber Interrupt Enable 1b.14 Receive Error Interrupt Enable 1b.13 Page Received Interrupt Enable 1b.12 Parallel Detect Fault Interrupt Enable 1b.11 Link Partner Acknowledge Interrupt Enable 1b ...
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... KS8721B/BT Address Name 1f.6 Enable Pause (Flow-Control Result) 1f.5 PHY Isolate 1f.4:2 Operation Mode Indication [000] = still in auto-negotiation 1f.1 Enable SQE Test 1f.0 Disable Data Scrambling Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “ ...
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... KS8721B/BT Absolute Maximum Ratings Supply Voltage ( DDC DD_PLL DD_TX DD_RCV V ) ................................................... –0.5V to +3.0V DD_RX (V ) .................................................... –0.5V to +4.0V DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ............................................ –0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270°C Storage Temperature (T ) ....................... –55°C to +150°C S Electrical Characteristics V = 2.5V ±5 0°C to +70°C; unless noted; bold values indicate –40°C ≤ T ...
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... KS8721B/BT Symbol Parameter 10BaseTX Receive R RX+/RX– Differential IN Input Resistance V Squelch Threshold SQ 10BaseTX Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage P Jitters Added Rise/Fall Time r t Clock Outputs X1, X2 Crystal Oscillator RXC Receive Clock, 100TX 100 RXC Receive Clock, 10T ...
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... KS8721B/BT Timing Diagrams TXC TXEN TXD[3:0] CRS TXP/TXM SQE Timing TXC TXEN COL Symbol Parameter t TXD [3:0] Set-Up to TXC High SU1 t TXEN Set-Up to TXC High SU2 t TXD [3:0] Hold After TXC High HD1 t TXEN Hold After TXC High HD2 t TXEN High to CRS Asserted Latency ...
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... KS8721B/BT TXC TXEN TXD[3:0], TXER CRS TX+/TX- Symbol Parameter t TXD [3:0] Set-Up to TXC High SU1 t TXEN Set-Up to TXC High SU2 t TXD [3:0] Hold After TXC High HD1 t TXER Hold After TXC High HD2 t TXEN Hold After TXC High HD3 t TXEN High to CRS Asserted Latency ...
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... KS8721B/BT Start of RX+/RX- Stream CRS RXDV RXD[3:0] RXER RXC Symbol Parameter t RXC Period P t RXC Pulse Width WL t RXC Pulse Width WH t RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC SU t RXD [3:0], RXER, RXDV Hold from Rising Edge of RXC HD t CRS to RXD Latency Aligned ...
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... KS8721B/BT TX+/TX- TX+/TX- Figure 7. Auto-Negotiation/Fast Link Pulse Timing Symbol Parameter t FLP Burst to FLP Burst BTB t FLP Burst Width FLPW t Clock/Data Pulse Width PW t Clock Pulse to Data Pulse CTD t Clock Pulse to Clock Pulse CTC Number of Clock/Data Pulses per Burst Table 5. Auto-Negotiation/Fast Link Pulse Timing ...
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... KS8721B/BT MDC MDIO (Into Chip) MDIO (Out of Chip) Symbol Parameter t MDC Period P t MDIO Set-Up to MDC (MDIO as input) MD1 t MDIO Hold after MDC (MDIO as input) MD2 t MDC to MDIO Valid (MDIO as output) MD3 M9999-041405 MD1 MD2 Valid Data t MD3 Figure 8. Serial Management Interface Timing Table 6 ...
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... Reset to Strap-In Pin Output rc Reset Circuit Diagram Micrel recommendeds the following discrete reset circuit as shown in Figure 10 when powering up the KS8721B/BT device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 11. ...
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... KS8721B/BT Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max ...
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... KS8721B/BT Package Information April 2005 48-Pin SSOP (SM) 31 Micrel, Inc. M9999-041405 ...
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... KS8721B/BT MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...