KS8721B Micrel Inc, KS8721B Datasheet - Page 9

• Manufacturer Part Number: KS8721B
• Description: Special Function IC
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KS8721B

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 576-1006 - BOARD EVAL EXPERIMENT KS8721B
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

Strapping Options
Note 1.
Note 2.
Note 3.
April 2005
KS8721B/BT
Pin Number
11
21
22
6,5,
9
4,3
25
27
28
29
30
(3)
(3)
(3)
(3)
Strap-in is latched during power-up or reset.
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset.
It is rcommended that an external pull down via 1kΩ resistor be used in these applications to augment the 8721's internal pull down.
PHYAD[4:1]/
PCS_LPBK/
ISO/RXER
NWAYEN/
Pin Name
RMII_BTB
RMII/COL
PHYAD0/
DUPLEX/
RXD[0:3]
SPD100/
No FEF/
RXDV
LED1
LED2
LED3
INT#
CRS
PD#
(Note 1)
Type
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu
(Note 2)
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
9
M9999-041405
Micrel, Inc.