KS8721B Micrel Inc, KS8721B Datasheet - Page 29
![Special Function IC](/photos/6/84/68448/576-48-ssop_sml.jpg)
KS8721B
Manufacturer Part Number
KS8721B
Description
Special Function IC
Manufacturer
Micrel Inc
Type
Transceiverr
Specifications of KS8721B
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Number Of Drivers/receivers
1/1
Protocol
MII, RMII
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
576-1006 - BOARD EVAL EXPERIMENT KS8721B
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KS8721B
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Part Number:
KS8721BL
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Company:
Part Number:
KS8721BT
Manufacturer:
LUCENT
Quantity:
560
Part Number:
KS8721BT
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Part Number:
KS8721BTR
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Symbol
Symbol
t
t
t
t
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 10 when powering up the KS8721B/BT device.
For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the
reset circuit as shown in Figure 11.
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/
FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO
voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
March 2006
sr
sr
sr
cs
ch
rc
Parameter
Parameter
Stable Supply Voltages to Reset High
Stable Supply Voltages to Reset High
Stable Supply Voltages to Reset High
Stable Supply Voltages to Reset High
Stable Supply Voltages to Reset High
Stable Supply Voltages to Reset High
Stable Supply Voltages to Reset High
Confi guration Set-Up Time
Confi guration Set-Up Time
Confi guration Set-Up Time
Confi guration Set-Up Time
Confi guration Set-Up Time
Confi guration Set-Up Time
Confi guration Hold Time
Confi guration Hold Time
Confi guration Hold Time
Confi guration Hold Time
Confi guration Hold Time
Confi guration Hold Time
Reset to Strap-In Pin Output
Reset to Strap-In Pin Output
Reset to Strap-In Pin Output
Reset to Strap-In Pin Output
Reset to Strap-In Pin Output
Reset to Strap-In Pin Output
Figure 11. Recommended Circuit for Interfacing with CPU/FPGA Reset
Output Pin
Strap-In
Voltage
RST_N
Strap-In /
Supply
Value
KS8721B/BT
Figure 10. Recommended Reset Circuit.
Table 7. Reset Timing Parameters
RST
KS8721B/BT
Figure 9. Reset Timing
D1
D1: 1N4148
RST
10µF
VCC
tsr
C
29
D1
R
10k
tcs
10µF
VCC
D2
C
tch
D1, D2: 1N4148
trc
R
10k
RST_OUT_n
CPU/FPGA
Min
Min
Min
Min
10
10
10
10
10
10
10
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
Typ
Typ
Typ
Typ
Max
Max
Max
Max
M9999-030106
Units
Units
Units
Units
ms
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs