LM12H458CIV National Semiconductor, LM12H458CIV Datasheet - Page 26

• Manufacturer Part Number: LM12H458CIV
• Description: A/D Converter (A-D) IC
• Manufacturer: National Semiconductor

Specifications of LM12H458CIV

• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 1
• Number Of Elements: 1
• Sample Rate: 182KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: ±0.75LSB
• Integral Nonlinearity Error: ±1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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2.0 Internal User-Programmable Registers
Note 21: LM12454 (Refer toTable 2).
Note 22: LM12(H)458 only. Must be set to “0” for the LM12454.
A4 A3 A2 A1 A0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
to
to
to
to
to
to
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
FIGURE 14. LM12(H)454/8 Memory Map for 8-Bit Wide Data Bus (BW = “1” and Test Bit = “0”)
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Instruction RAM
(RAM Pointer =
Configuration
Limit Status
Conversion
Instruction
Instruction
Purpose
Pointer =
Pointer =
Register
Interrupt
Register
Interrupt
Register
Register
Register
Enable
Status
(RAM
(RAM
Timer
FIFO
RAM
RAM
00)
01)
10)
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W I/O Sel
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
INST7
INT7
Number of Conversions in Conversion FIFO to
D7
Actual Number of Conversions Results in
V
Address or Sign
IN−
Auto Zero
(Note 21)
26
(MUXOUT−)
Acquisition Time
INST6
INT6
D6
Don’t Care
Conversion FIFO
Generate INT2
ec
(Continued)
Don’t Care
Don’t Care
Don’t Care
INST5
Chan
Mask
INT5
D5
Timer Preset: High Byte
Timer Preset: Low Byte
Conversion Data: LSBs
Comparison Limit #1
Comparison Limit #2
Limit #1 Status
Limit #2 Status
Stand-
INST4
INT4
Sign
D4
by
V
IN+
(Note 21)
(MUXOUT+)
Full Cal
Watch-
INST3
DIAG
(Note
INT3
dog
22)
D3
Conversion Data: MSBs
INST2 INST1 INST0
Test =
Auto-
Address of Sequencer
Sequencer Address to
INT2
8/12
Zero
D2
0
Instruction being
Generate INT1
Executed
Pause
Reset
Timer
INT1
RAM Pointer
>
>
>
D1
/
/
/
<
<
<
Loop
Sync
INT0
Sign
Sign
Sign
Start
D0