LM96000CIMT National Semiconductor, LM96000CIMT Datasheet - Page 17

• Manufacturer Part Number: LM96000CIMT
• Description: IC,Data Acquisition System,7-CHANNEL,8-BIT,TSSOP,24PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LM96000CIMT

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register
Address
54h
55h
56h
57h
58h
59h
5Ah
5Bh
Register
Address
50h
51h
52h
53h
Functional Description
If an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit
register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automatically by the
LM96000 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote1− and Remote1+ inputs
exceeds the Processor (Zone1) High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature
limits in these registers are represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown below in Table 3.
Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
4.13 Registers 54-5Bh: Fan Tachometer Low Limit
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the
Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so care should be taken in software
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/
Write
R/W
R/W
R/W
R/W
Register
Name
Tach1 Minimum LSB
Tach1 Minimum MSB
Tach2 Minimum LSB
Tach2 Minimum MSB
Tach3 Minimum LSB
Tach3 Minimum MSB
Tach4 Minimum LSB
Tach4 Minimum MSB
Register
Name
Processor (Zone2)
Low Temp
Processor (Zone2)
High Temp
Processor (Zone3)
Low Temp
Processor (Zone3)
High Temp
Temperature
TABLE 3. Temperature Limits vs Register Settings
−127˚C
−50˚C
127˚C
50˚C
(Continued)
0˚C
.
.
.
.
.
.
.
.
.
.
.
.
Bit 7
(MSB)
7
7
7
7
Bit 7
(MSB)
7
15
7
15
7
15
7
15
Reading (Decimal)
Bit 6
6
6
6
6
Bit 6
6
14
6
14
6
14
6
14
−127
−50
127
50
0
.
.
.
.
.
.
.
.
.
.
.
.
17
Bit 5
5
5
5
5
Bit 5
5
13
5
13
5
13
5
13
Bit 4
4
4
4
4
Bit 4
4
12
4
12
4
12
4
12
Reading (Hex)
CEh
7Fh
81h
00h
32h
Bit 3
3
3
3
3
.
.
.
.
.
.
.
.
.
.
.
.
Bit 3
3
11
3
11
3
11
3
11
Bit 2
2
2
2
2
Bit 2
2
10
2
10
2
10
2
10
Bit 1
1
1
1
1
Bit 1
1
9
1
9
1
9
1
9
Bit 0
(LSB)
0
0
0
0
Bit 0
(LSB)
0
8
0
8
0
8
0
8
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Default
Value
81h
7Fh
81h
7Fh
Default
Value
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh