LM96000CIMT National Semiconductor, LM96000CIMT Datasheet - Page 8

• Manufacturer Part Number: LM96000CIMT
• Description: IC,Data Acquisition System,7-CHANNEL,8-BIT,TSSOP,24PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LM96000CIMT

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Note 14: Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t
the SMBDAT pin to a high impedance state.
Functional Description
1.0 SMBUS
The LM96000 is compatible with devices that are compliant to the SMBus 2.0 specification. More information on this bus can be
found at: http://www.smbus.org/. Compatibility of SMBus2.0 to other buses is discussed in the SMBus 2.0 specification.
1.1 Addressing
LM96000 is designed to be used primarily in desktop systems that require only one monitoring device.
If only one LM96000 is used on the motherboard, the designer should be sure that the Address Enable/PWM3 pin is High during
the first SMBus communication addressing the LM96000. Address Enable/PWM3 is an open drain I/O pin that at power-on
defaults to the input state of Address Enable. A maximum of 10k pull-up resistance on Address Enable/PWM3 is required to
assure that the SMBus address of the device will be locked at 010 1110b, which is the default address of the LM96000.
During the first SMBus communication TACH4 and PWM3 can be used to change the SMBus address of the LM96000 to
0101101b or 0101100b. LM96000 address selection procedure:
In this way, up to three LM96000 devices can exists on an SMBus at any time. Multiple LM96000 devices can be used to monitor
additional processors and temperature zones. When using the non-default addresses additional circuitry will be required if TACH4
and PWM3 require to function correctly. Such circuitry could consist of GPIO pins from a micro-controller. During the first
communication the micro-controller would drive the Address Enable and Address Select pins to the proper state for the required
address. After the first SMBus communication the micro-controller would drive it’s pins into TRISTATE allowing TACH4 and
PWM3 to operate correctly.
2.0 FAN REGISTER DEVICE SET-UP
The BIOS will follow the following steps to configure the fan registers on the LM96000. The registers corresponding to each
function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS
to the fan limit and parameter registers during configuration, the LM96000 will continue to operate based on default values until
the START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting
the START bit to 1, the LM96000 will operate using the values that were set by the BIOS in the fan control limit and parameter
registers (adress 5Ch through 6Eh).
A 10 kΩ pull-down resistor to ground on the Address Enable/PWM3 pin is required. Upon power up, the LM96000 will be placed
into Address Enable mode and assign itself an SMBus address according to the state of the Address Select input. The
LM96000 will latch the address during the first valid SMBus transaction in which the first five bits of the targeted address match
those of the LM96000 address, 0 1011b. This feature eliminates the possibility of a glitch on the SMBus interfering with address
selection. When the PWM3/Address Enable pin is not used to change the SMBus address of the LM96000, it will remain in a
high state until the first communication with the LM96000. After the first SMBus transaction is completed PWM3 and TACH4 will
return to normal operation.
Address Enable
0
0
1
Address Select
0
1
X
Board Implementation
Pulled to ground through a 10 kΩ resistor
Pulled to 3.3V or to GND through a 10 kΩ resistor
Pulled to 3.3V through a 10 kΩ resistor
8
TIMEOUT
will reset the LM96000’s SMBus state machine, therefore setting
20084604
SMBus Address
010 1100b, 2Ch
010 1101b, 2Dh
010 1110b, 2Eh