PIC16F870-E/SO Microchip Technology, PIC16F870-E/SO Datasheet - Page 102
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PIC16F870-E/SO
Manufacturer Part Number
PIC16F870-E/SO
Description
28 PIN, 3.5KB ENH FLASH, 128 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F870-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 102 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
6.3
6.3.1
6.3.2
DS31006A-page 6-8
General Purpose Registers (GPR)
Special Function Registers (SFR)
Data Memory Organization
Data memory is made up of the Special Function Registers (SFR) area, and the General Pur-
pose Registers (GPR) area. The SFRs control the operation of the device, while GPRs are the
general area for data storage and scratch pad operations.
The data memory is banked for both the GPR and SFR areas. The GPR area is banked to allow
greater than 96 bytes of general purpose RAM to be addressed. SFRs are for the registers that
control the peripheral and core functions. Banking requires the use of control bits for bank selec-
tion. These control bits are located in the STATUS Register (STATUS<7:5>).
one of the data memory map organizations, this organization is device dependent.
To move values from one register to another register, the value must pass through the W register.
This means that for all register-to-register moves, two instruction cycles are required.
The entire data memory can be accessed either directly or indirectly. Direct addressing may
require the use of the RP1:RP0 bits. Indirect addressing requires the use of the File Select Reg-
ister (FSR). Indirect addressing uses the Indirect Register Pointer (IRP) bit of the STATUS regis-
ter for accesses into the Bank0 / Bank1 or the Bank2 / Bank3 areas of data memory.
Some Mid-Range MCU devices have banked memory in the GPR area. GPRs are not initialized
by a Power-on Reset and are unchanged on all other resets.
The register file can be accessed either directly, or using the File Select Register FSR, indirectly.
Some devices have areas that are shared across the data memory banks, so a read / write to
that area will appear as the same location (value) regardless of the current bank. We refer to this
area as the Common RAM.
The SFRs are used by the CPU and Peripheral Modules for controlling the desired operation of
the device. These registers are implemented as static RAM.
The SFRs can be classified into two sets, those associated with the “core” function and those
related to the peripheral functions. Those registers related to the “core” are described in this sec-
tion, while those related to the operation of the peripheral features are described in the section
of that peripheral feature.
All Mid-Range MCU devices have banked memory in the SFR area. Switching between these
banks requires the RP0 and RP1 bits in the STATUS register to be configured for the desired
bank. Some SFRs are initialized by a Power-on Reset and other resets, while other SFRs are
unaffected.
The register file can be accessed either directly, or using the File Select Register FSR, indirectly.
Note:
The Special Function Register (SFR) Area may have General Purpose Registers
(GPRs) mapped in these locations.
1997 Microchip Technology Inc.
Figure 6-5
shows
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